File: bug18491-optsize.ll

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llvm-toolchain-15 1%3A15.0.6-4
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; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: {{.balign 4|.p2align 2}}
; CHECK: {{.balign 4|.p2align 2}}
; CHECK: {{.balign 4|.p2align 2}}

target triple = "hexagon"

@g0 = global i32 4, align 4
@g1 = global i32 4, align 4
@g2 = global i32 4, align 4
@g3 = global i32 4, align 4

; Function Attrs: nounwind optsize
define void @f0(i32 %a0) #0 {
b0:
  store i32 1, i32* @g0, align 4
  ret void
}

; Function Attrs: nounwind optsize
define void @f1(i32 %a0) #0 {
b0:
  store i32 1, i32* @g0, align 4
  store i32 2, i32* @g1, align 4
  store i32 3, i32* @g2, align 4
  store i32 4, i32* @g3, align 4
  ret void
}

; Function Attrs: nounwind optsize readnone
define i32 @f2(i32 %a0, i8** nocapture readnone %a1) #1 {
b0:
  ret i32 %a0
}

attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" }
attributes #1 = { nounwind optsize readnone "target-cpu"="hexagonv60" }