File: misaligned-access.ll

package info (click to toggle)
llvm-toolchain-15 1%3A15.0.6-4
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,554,644 kB
  • sloc: cpp: 5,922,452; ansic: 1,012,136; asm: 674,362; python: 191,568; objc: 73,855; f90: 42,327; lisp: 31,913; pascal: 11,973; javascript: 10,144; sh: 9,421; perl: 7,447; ml: 5,527; awk: 3,523; makefile: 2,520; xml: 885; cs: 573; fortran: 567
file content (19 lines) | stat: -rw-r--r-- 456 bytes parent folder | download | duplicates (11) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
 
; RUN: llc -march=hexagon < %s
; Check that the mis-aligned load doesn't cause compiler to assert.

@g0 = common global i32 0, align 4

declare i32 @f0(i64) #0

define i32 @f1() #0 {
b0:
  %v0 = alloca i32, align 4
  %v1 = load i32, i32* @g0, align 4
  store i32 %v1, i32* %v0, align 4
  %v2 = bitcast i32* %v0 to i64*
  %v3 = load i64, i64* %v2, align 8
  %v4 = call i32 @f0(i64 %v3)
  ret i32 %v4
}

attributes #0 = { nounwind "target-cpu"="hexagonv5" }