File: wrong-stack-slot-rv32.mir

package info (click to toggle)
llvm-toolchain-15 1%3A15.0.6-4
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,554,644 kB
  • sloc: cpp: 5,922,452; ansic: 1,012,136; asm: 674,362; python: 191,568; objc: 73,855; f90: 42,327; lisp: 31,913; pascal: 11,973; javascript: 10,144; sh: 9,421; perl: 7,447; ml: 5,527; awk: 3,523; makefile: 2,520; xml: 885; cs: 573; fortran: 567
file content (94 lines) | stat: -rw-r--r-- 3,062 bytes parent folder | download
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+m,+v  -o - %s \
# RUN:   -start-before=prologepilog | FileCheck %s
#
# These tests check that we are assigning the right stack slot to GPRs and to
# vector registers (VRs). If this test changes, make sure there is no overlap
# between slots for GPRs and VRs.
--- |
  define void @foo() #0 {
  ; CHECK-LABEL: foo:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    addi sp, sp, -32
  ; CHECK-NEXT:    sw s9, 28(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    csrr a1, vlenb
  ; CHECK-NEXT:    slli a1, a1, 1
  ; CHECK-NEXT:    sub sp, sp, a1
  ; CHECK-NEXT:    sw a0, 8(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    addi a0, sp, 16
  ; CHECK-NEXT:    vs2r.v v30, (a0) # Unknown-size Folded Spill
  ; CHECK-NEXT:    csrr a0, vlenb
  ; CHECK-NEXT:    slli a0, a0, 1
  ; CHECK-NEXT:    add sp, sp, a0
  ; CHECK-NEXT:    lw s9, 28(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    addi sp, sp, 32
  ; CHECK-NEXT:    ret
  entry:
    ret void
  }

  define void @rvv_clobbers_callee_save() #0 {
  ; CHECK-LABEL: rvv_clobbers_callee_save:
  ; CHECK:       # %bb.0: # %entry
  ; CHECK-NEXT:    addi sp, sp, -80
  ; CHECK-NEXT:    sw ra, 76(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    sw s0, 72(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    sw s9, 68(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    addi s0, sp, 80
  ; CHECK-NEXT:    csrr a1, vlenb
  ; CHECK-NEXT:    slli a1, a1, 1
  ; CHECK-NEXT:    sub sp, sp, a1
  ; CHECK-NEXT:    andi sp, sp, -32
  ; CHECK-NEXT:    sw a0, 32(sp) # 4-byte Folded Spill
  ; CHECK-NEXT:    addi a0, sp, 64
  ; CHECK-NEXT:    vs2r.v v30, (a0) # Unknown-size Folded Spill
  ; CHECK-NEXT:    addi sp, s0, -80
  ; CHECK-NEXT:    lw ra, 76(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    lw s0, 72(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    lw s9, 68(sp) # 4-byte Folded Reload
  ; CHECK-NEXT:    addi sp, sp, 80
  ; CHECK-NEXT:    ret
  entry:
    ret void
  }

  attributes #0 = { nounwind }
...
---
name:            foo
alignment:       2
frameInfo:
  maxAlignment:    8
stack:
  - { id: 0, type: spill-slot, size: 4, alignment: 4 }
  - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10, $v30m2

    $x25 = COPY $x10
    SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
    PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
    PseudoRET

...
---
name:            rvv_clobbers_callee_save
alignment:       2
frameInfo:
  maxAlignment:    8
stack:
  - { id: 0, type: spill-slot, size: 4, alignment: 32 }
  - { id: 1, type: spill-slot, size: 16, alignment: 8, stack-id: scalable-vector }
machineFunctionInfo: {}
body:             |
  bb.0.entry:
    liveins: $x10, $v30m2

    $x25 = COPY $x10
    SW renamable $x25, %stack.0, 0 :: (store (s32) into %stack.0)
    PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
    PseudoRET

...