1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
|
# RUN: llc -mtriple=s390x-linux-gnu -start-before=prologepilog %s -o - -mcpu=z14 \
# RUN: -debug-only=prologepilog -print-after=prologepilog -verify-machineinstrs 2>&1 \
# RUN: | FileCheck %s
# REQUIRES: asserts
#
# Test that stack objects are ordered in a good way with respect to the
# displacement operands of users.
--- |
define void @f1() { ret void }
define void @f2() { ret void }
define void @f3() { ret void }
define void @f4() { ret void }
define void @f5() { ret void }
define void @f6() { ret void }
...
### Test that %stack.0 is placed close to its D12 user.
# CHECK: alloc FI(1) at SP[-4255]
# CHECK-NEXT: alloc FI(0) at SP[-4271]
# CHECK-NEXT: alloc FI(2) at SP[-4280]
# CHECK-NEXT: alloc FI(3) at SP[-4288]
# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
# CHECK-NEXT: # Machine code for function f1: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK-NOT: LAY
# CHECK: VL32
---
name: f1
tracksRegLiveness: true
stack:
- { id: 0, size: 16 }
- { id: 1, size: 4095 }
machineFunctionInfo: {}
body: |
bb.0:
renamable $f0s = VL32 %stack.0, 0, $noreg
Return
...
### Test that %stack.1 is placed close to its D12 user.
# CHECK: alloc FI(0) at SP[-176]
# CHECK-NEXT: alloc FI(1) at SP[-4271]
# CHECK-NEXT: alloc FI(2) at SP[-4280]
# CHECK-NEXT: alloc FI(3) at SP[-4288]
# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
# CHECK-NEXT: # Machine code for function f2: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK-NOT: LAY
# CHECK: VL32
---
name: f2
tracksRegLiveness: true
stack:
- { id: 0, size: 16 }
- { id: 1, size: 4095 }
machineFunctionInfo: {}
body: |
bb.0:
renamable $f0s = VL32 %stack.1, 3916, $noreg
Return
...
### Swap the order of the objects so that both accesses are in range.
# CHECK: alloc FI(1) at SP[-8350]
# CHECK-NEXT: alloc FI(0) at SP[-12445]
# CHECK-NEXT: alloc FI(2) at SP[-12456]
# CHECK-NEXT: alloc FI(3) at SP[-12464]
# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
# CHECK-NEXT: # Machine code for function f3: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK-NOT: LAY
# CHECK: VL32
# CHECK-NOT: LAY
# CHECK: LEY
---
name: f3
tracksRegLiveness: true
stack:
- { id: 0, size: 4095 }
- { id: 1, size: 8190 }
machineFunctionInfo: {}
body: |
bb.0:
renamable $f0s = VL32 %stack.0, 0, $noreg
renamable $f0s = LE %stack.1, 0, $noreg
Return
...
### Reorder the objects so that all accesses are in range.
# CHECK: alloc FI(0) at SP[-8350]
# CHECK-NEXT: alloc FI(2) at SP[-16540]
# CHECK-NEXT: alloc FI(3) at SP[-24730]
# CHECK-NEXT: alloc FI(1) at SP[-26777]
# CHECK-NEXT: alloc FI(4) at SP[-28824]
# CHECK-NEXT: alloc FI(5) at SP[-28832]
# CHECK-NEXT: alloc FI(6) at SP[-28840]
# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
# CHECK-NEXT: # Machine code for function f4: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK-NOT: LAY
# CHECK: LEY
# CHECK-NEXT: VL32
# CHECK-NEXT: LEY
# CHECK-NEXT: LEY
# CHECK-NEXT: VL32
---
name: f4
tracksRegLiveness: true
stack:
- { id: 0, size: 8190 }
- { id: 1, size: 2047 }
- { id: 2, size: 8190 }
- { id: 3, size: 8190 }
- { id: 4, size: 2047 }
machineFunctionInfo: {}
body: |
bb.0:
renamable $f2s = LE %stack.0, 0, $noreg
renamable $f0s = VL32 %stack.1, 0, $noreg
renamable $f3s = LEY %stack.2, 0, $noreg
renamable $f4s = LE %stack.3, 0, $noreg
renamable $f1s = VL32 %stack.4, 0, $noreg
Return
...
### Reorder the objects so that the VL32 object is in range and the LYs are
### shortened to Ls (STOC cannot be shortened).
# CHECK: alloc FI(0) at SP[-8350]
# CHECK-NEXT: alloc FI(1) at SP[-16540]
# CHECK-NEXT: alloc FI(2) at SP[-24730]
# CHECK-NEXT: alloc FI(3) at SP[-26777]
# CHECK-NEXT: alloc FI(4) at SP[-26792]
# CHECK-NEXT: alloc FI(5) at SP[-26800]
# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
# CHECK-NEXT: # Machine code for function f5: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK-NOT: LAY
# CHECK: $r1l = L $r15
# CHECK-NEXT: $r1l = L $r15
# CHECK-NEXT: IMPLICIT_DEF
# CHECK-NEXT: STOC
# CHECK-NEXT: STOC
# CHECK-NEXT: VL32
---
name: f5
tracksRegLiveness: true
stack:
- { id: 0, size: 8190 }
- { id: 1, size: 8190 }
- { id: 2, size: 8190 }
- { id: 3, size: 2047 }
machineFunctionInfo: {}
body: |
bb.0:
$r1l = LY %stack.2, 0, $noreg
$r1l = LY %stack.2, 0, $noreg
$cc = IMPLICIT_DEF
STOC $r1l, %stack.0, 0, 14, 8, implicit $cc
STOC $r1l, %stack.1, 0, 14, 8, implicit $cc
renamable $f3s = VL32 %stack.3, 0, $noreg
Return
...
### Test handling of a variable sized object.
# CHECK: alloc FI(1) at SP[-476]
# CHECK-NEXT: alloc FI(0) at SP[-776]
# CHECK-NEXT: alloc FI(2) at SP[-776]
# CHECK-NEXT: # *** IR Dump After Prologue/Epilogue Insertion & Frame Finalization
# CHECK-NEXT: # Machine code for function f6: IsSSA, NoPHIs, TracksLiveness, NoVRegs
# CHECK: $r15d = AGHI $r15d(tied-def 0), -776, implicit-def dead $cc
# CHECK: $r11d = LGR $r15d
# CHECK: renamable $r2d = ADJDYNALLOC renamable $r1d, 0, $noreg
# CHECK: VST64 renamable $f0d, $r11d, 160, $noreg
# CHECK: VST32 renamable $f1s, $r11d, 460, $noreg
# CHECK: VST32 killed renamable $f0s, killed renamable $r2d, 0, $noreg
---
name: f6
tracksRegLiveness: true
stack:
- { id: 0, size: 300 }
- { id: 1, size: 316 }
- { id: 2, type: variable-sized }
machineFunctionInfo: {}
body: |
bb.0 (%ir-block.0):
liveins: $f0d, $f0s, $f1s, $r2l
renamable $r2l = KILL $r2l, implicit-def $r2d
renamable $r1d = RISBGN undef renamable $r1d, killed renamable $r2d, 30, 189, 2
renamable $r0d = nuw LA killed renamable $r1d, 7, $noreg
renamable $r0d = RISBGN undef renamable $r0d, killed renamable $r0d, 29, 188, 0
renamable $r1d = SGRK $r15d, killed renamable $r0d, implicit-def dead $cc
renamable $r2d = ADJDYNALLOC renamable $r1d, 0, $noreg
$r15d = COPY killed renamable $r1d
VST64 renamable $f0d, %stack.0, 0, $noreg
VST32 renamable $f1s, %stack.1, 0, $noreg
VST32 killed renamable $f0s, killed renamable $r2d, 0, $noreg
Return
...
|
