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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
declare void @llvm.masked.store.v512f32.p0v512f32(<512 x float>, <512 x float>*, i32 immarg, <512 x i1>)
define fastcc void @vec_mstore_v512f32(<512 x float>* %P, <512 x float> %V, <512 x i1> %M) {
; CHECK-LABEL: vec_mstore_v512f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 256
; CHECK-NEXT: lvl %s1
; CHECK-NEXT: vstu %v0, 8, %s0
; CHECK-NEXT: vshf %v0, %v0, %v0, 4
; CHECK-NEXT: lea %s0, 4(, %s0)
; CHECK-NEXT: vstu %v0, 8, %s0
; CHECK-NEXT: b.l.t (, %s10)
call void @llvm.masked.store.v512f32.p0v512f32(<512 x float> %V, <512 x float>* %P, i32 16, <512 x i1> %M)
ret void
}
declare void @llvm.masked.store.v512i32.p0v512i32(<512 x i32>, <512 x i32>*, i32 immarg, <512 x i1>)
define fastcc void @vec_mstore_v512i32(<512 x i32>* %P, <512 x i32> %V, <512 x i1> %M) {
; CHECK-LABEL: vec_mstore_v512i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s1, 4(, %s0)
; CHECK-NEXT: lea %s2, 256
; CHECK-NEXT: lvl %s2
; CHECK-NEXT: vstl %v0, 8, %s1
; CHECK-NEXT: vshf %v0, %v0, %v0, 0
; CHECK-NEXT: vstl %v0, 8, %s0
; CHECK-NEXT: b.l.t (, %s10)
call void @llvm.masked.store.v512i32.p0v512i32(<512 x i32> %V, <512 x i32>* %P, i32 16, <512 x i1> %M)
ret void
}
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