1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define float @test_fptrunc(double %in) {
%res = fptrunc double %in to float
ret float %res
}
...
---
name: test_fptrunc
alignment: 16
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
- { id: 3, class: vecr }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0
; ALL-LABEL: name: test_fptrunc
; ALL: liveins: $xmm0
; ALL: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
; ALL: [[COPY1:%[0-9]+]]:fr64 = COPY [[COPY]]
; ALL: %2:fr32 = nofpexcept CVTSD2SSrr [[COPY1]], implicit $mxcsr
; ALL: [[COPY2:%[0-9]+]]:vr128 = COPY %2
; ALL: $xmm0 = COPY [[COPY2]]
; ALL: RET 0, implicit $xmm0
%1:vecr(s128) = COPY $xmm0
%0:vecr(s64) = G_TRUNC %1(s128)
%2:vecr(s32) = G_FPTRUNC %0(s64)
%3:vecr(s128) = G_ANYEXT %2(s32)
$xmm0 = COPY %3(s128)
RET 0, implicit $xmm0
...
|
