File: vop3p_opsel.txt

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llvm-toolchain-15 1%3A15.0.6-4
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# RUN: llvm-mc -arch=amdgcn -mcpu=gfx900 -disassemble -show-encoding < %s | FileCheck %s

# Check that we can disassemble opcodes w/o src2 with any op_sel_hi value for src2

# CHECK: v_pk_add_f16 v5, v1, v2 ; encoding: [0x05,0x40,0x8f,0xd3,0x01,0x05,0x02,0x18]
0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x18

# CHECK: v_pk_add_f16 v5, v1, v2 ; encoding: [0x05,0x40,0x8f,0xd3,0x01,0x05,0x02,0x18]
0x05,0x40,0x8f,0xd3,0x01,0x05,0x02,0x18

# CHECK: v_pk_add_f16 v5, v1, v2 op_sel_hi:[0,0] ; encoding: [0x05,0x40,0x8f,0xd3,0x01,0x05,0x02,0x00]
0x05,0x00,0x8f,0xd3,0x01,0x05,0x02,0x00

# CHECK: v_pk_add_f16 v5, v1, v2 op_sel_hi:[0,0] ; encoding: [0x05,0x40,0x8f,0xd3,0x01,0x05,0x02,0x00]
0x05,0x40,0x8f,0xd3,0x01,0x05,0x02,0x00