File: invalid-instruction.txt

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llvm-toolchain-15 1%3A15.0.6-4
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# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+c < %s 2>&1 | FileCheck %s
# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+c < %s 2>&1 | FileCheck %s
#
# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
# for the RISC-V assembly language.

# This should not decode as c.addi16sp with 0 imm when compression is enabled.
[0x01 0x61]
# CHECK: warning: invalid instruction encoding