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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 < %s | FileCheck %s
# Code snippet taken from PR48024.
stmxcsr -4(%rsp)
movl $-24577, %eax # imm = 0x9FFF
andl -4(%rsp), %eax
movl %eax, -8(%rsp)
ldmxcsr -8(%rsp)
retq
# CHECK: Iterations: 100
# CHECK-NEXT: Instructions: 600
# CHECK-NEXT: Total Cycles: 413
# CHECK-NEXT: Total uOps: 1300
# CHECK: Dispatch Width: 4
# CHECK-NEXT: uOps Per Cycle: 3.15
# CHECK-NEXT: IPC: 1.45
# CHECK-NEXT: Block RThroughput: 3.3
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 3 2 1.00 * U stmxcsr -4(%rsp)
# CHECK-NEXT: 1 1 0.25 movl $-24577, %eax
# CHECK-NEXT: 2 6 0.50 * andl -4(%rsp), %eax
# CHECK-NEXT: 1 1 1.00 * movl %eax, -8(%rsp)
# CHECK-NEXT: 3 7 1.00 * * U ldmxcsr -8(%rsp)
# CHECK-NEXT: 3 7 1.00 U retq
# CHECK: Resources:
# CHECK-NEXT: [0] - HWDivider
# CHECK-NEXT: [1] - HWFPDivider
# CHECK-NEXT: [2] - HWPort0
# CHECK-NEXT: [3] - HWPort1
# CHECK-NEXT: [4] - HWPort2
# CHECK-NEXT: [5] - HWPort3
# CHECK-NEXT: [6] - HWPort4
# CHECK-NEXT: [7] - HWPort5
# CHECK-NEXT: [8] - HWPort6
# CHECK-NEXT: [9] - HWPort7
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9]
# CHECK-NEXT: - - 1.99 1.50 1.66 1.67 2.00 1.52 1.99 1.67
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
# CHECK-NEXT: - - - - 0.16 - 1.00 1.00 - 0.84 stmxcsr -4(%rsp)
# CHECK-NEXT: - - 0.49 0.49 - - - 0.01 0.01 - movl $-24577, %eax
# CHECK-NEXT: - - 0.49 0.02 0.49 0.51 - 0.01 0.48 - andl -4(%rsp), %eax
# CHECK-NEXT: - - - - 0.17 - 1.00 - - 0.83 movl %eax, -8(%rsp)
# CHECK-NEXT: - - 1.00 0.01 0.33 0.67 - 0.49 0.50 - ldmxcsr -8(%rsp)
# CHECK-NEXT: - - 0.01 0.98 0.51 0.49 - 0.01 1.00 - retq
# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 01234
# CHECK: [0,0] DeeER. . . . . stmxcsr -4(%rsp)
# CHECK-NEXT: [0,1] DeE-R. . . . . movl $-24577, %eax
# CHECK-NEXT: [0,2] .DeeeeeeER. . . . andl -4(%rsp), %eax
# CHECK-NEXT: [0,3] .D======eER . . . movl %eax, -8(%rsp)
# CHECK-NEXT: [0,4] . D=====eeeeeeeER . . ldmxcsr -8(%rsp)
# CHECK-NEXT: [0,5] . DeeeeeeeE----R . . retq
# CHECK-NEXT: [1,0] . D====eeE----R . . stmxcsr -4(%rsp)
# CHECK-NEXT: [1,1] . DeE---------R . . movl $-24577, %eax
# CHECK-NEXT: [1,2] . DeeeeeeE---R . . andl -4(%rsp), %eax
# CHECK-NEXT: [1,3] . D======eE--R . . movl %eax, -8(%rsp)
# CHECK-NEXT: [1,4] . .D=====eeeeeeeER . ldmxcsr -8(%rsp)
# CHECK-NEXT: [1,5] . . D=eeeeeeeE---R . retq
# CHECK-NEXT: [2,0] . . D====eeE----R . stmxcsr -4(%rsp)
# CHECK-NEXT: [2,1] . . DeE---------R . movl $-24577, %eax
# CHECK-NEXT: [2,2] . . DeeeeeeE---R . andl -4(%rsp), %eax
# CHECK-NEXT: [2,3] . . D======eE--R . movl %eax, -8(%rsp)
# CHECK-NEXT: [2,4] . . D=====eeeeeeeER ldmxcsr -8(%rsp)
# CHECK-NEXT: [2,5] . . .DeeeeeeeE----R retq
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 3 3.7 1.0 2.7 stmxcsr -4(%rsp)
# CHECK-NEXT: 1. 3 1.0 1.0 6.3 movl $-24577, %eax
# CHECK-NEXT: 2. 3 1.0 1.0 2.0 andl -4(%rsp), %eax
# CHECK-NEXT: 3. 3 7.0 0.0 1.3 movl %eax, -8(%rsp)
# CHECK-NEXT: 4. 3 6.0 0.0 0.0 ldmxcsr -8(%rsp)
# CHECK-NEXT: 5. 3 1.3 1.3 3.7 retq
# CHECK-NEXT: 3 3.3 0.7 2.7 <total>
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