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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +zkne -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=RV32ZKNE
// RV32ZKNE-LABEL: @aes32esi(
// RV32ZKNE-NEXT: entry:
// RV32ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZKNE-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
// RV32ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
// RV32ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
// RV32ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
// RV32ZKNE-NEXT: ret i32 [[TMP2]]
//
int aes32esi(int rs1, int rs2) {
return __builtin_riscv_aes32esi_32(rs1, rs2, 3);
}
// RV32ZKNE-LABEL: @aes32esmi(
// RV32ZKNE-NEXT: entry:
// RV32ZKNE-NEXT: [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZKNE-NEXT: [[RS2_ADDR:%.*]] = alloca i32, align 4
// RV32ZKNE-NEXT: store i32 [[RS1:%.*]], ptr [[RS1_ADDR]], align 4
// RV32ZKNE-NEXT: store i32 [[RS2:%.*]], ptr [[RS2_ADDR]], align 4
// RV32ZKNE-NEXT: [[TMP0:%.*]] = load i32, ptr [[RS1_ADDR]], align 4
// RV32ZKNE-NEXT: [[TMP1:%.*]] = load i32, ptr [[RS2_ADDR]], align 4
// RV32ZKNE-NEXT: [[TMP2:%.*]] = call i32 @llvm.riscv.aes32esmi(i32 [[TMP0]], i32 [[TMP1]], i8 3)
// RV32ZKNE-NEXT: ret i32 [[TMP2]]
//
int aes32esmi(int rs1, int rs2) {
return __builtin_riscv_aes32esmi_32(rs1, rs2, 3);
}
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