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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h>
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16mf4_f16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv1f16(<vscale x 1 x half> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret half [[TMP0]]
//
_Float16 test_vfmv_f_s_f16mf4_f16(vfloat16mf4_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16mf2_f16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv2f16(<vscale x 2 x half> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret half [[TMP0]]
//
_Float16 test_vfmv_f_s_f16mf2_f16(vfloat16mf2_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16m1_f16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv4f16(<vscale x 4 x half> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret half [[TMP0]]
//
_Float16 test_vfmv_f_s_f16m1_f16(vfloat16m1_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16m2_f16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv8f16(<vscale x 8 x half> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret half [[TMP0]]
//
_Float16 test_vfmv_f_s_f16m2_f16(vfloat16m2_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16m4_f16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv16f16(<vscale x 16 x half> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret half [[TMP0]]
//
_Float16 test_vfmv_f_s_f16m4_f16(vfloat16m4_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f16m8_f16(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call half @llvm.riscv.vfmv.f.s.nxv32f16(<vscale x 32 x half> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret half [[TMP0]]
//
_Float16 test_vfmv_f_s_f16m8_f16(vfloat16m8_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f32mf2_f32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv1f32(<vscale x 1 x float> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret float [[TMP0]]
//
float test_vfmv_f_s_f32mf2_f32(vfloat32mf2_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m1_f32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv2f32(<vscale x 2 x float> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret float [[TMP0]]
//
float test_vfmv_f_s_f32m1_f32(vfloat32m1_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m2_f32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv4f32(<vscale x 4 x float> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret float [[TMP0]]
//
float test_vfmv_f_s_f32m2_f32(vfloat32m2_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m4_f32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv8f32(<vscale x 8 x float> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret float [[TMP0]]
//
float test_vfmv_f_s_f32m4_f32(vfloat32m4_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f32m8_f32(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call float @llvm.riscv.vfmv.f.s.nxv16f32(<vscale x 16 x float> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret float [[TMP0]]
//
float test_vfmv_f_s_f32m8_f32(vfloat32m8_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m1_f64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv1f64(<vscale x 1 x double> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret double [[TMP0]]
//
double test_vfmv_f_s_f64m1_f64(vfloat64m1_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m2_f64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv2f64(<vscale x 2 x double> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret double [[TMP0]]
//
double test_vfmv_f_s_f64m2_f64(vfloat64m2_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m4_f64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv4f64(<vscale x 4 x double> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret double [[TMP0]]
//
double test_vfmv_f_s_f64m4_f64(vfloat64m4_t src) {
return __riscv_vfmv_f(src);
}
// CHECK-RV64-LABEL: @test_vfmv_f_s_f64m8_f64(
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call double @llvm.riscv.vfmv.f.s.nxv8f64(<vscale x 8 x double> [[SRC:%.*]])
// CHECK-RV64-NEXT: ret double [[TMP0]]
//
double test_vfmv_f_s_f64m8_f64(vfloat64m8_t src) {
return __riscv_vfmv_f(src);
}
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