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# NOTE: This file is Generic MIR translation of test/Analysis/DivergenceAnalysis/AMDGPU/always_uniform.ll test file
# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s
---
name: readfirstlane
body: |
bb.1:
; CHECK-LABEL: MachineUniformityInfo for function: readfirstlane
; CHECK: DIVERGENT: %{{[0-9]+}}
; CHECK-SAME:llvm.amdgcn.workitem.id.x
; CHECK-NOT: DIVERGENT: {{.*}}llvm.amdgcn.readfirstlane
%6:_(p1) = G_IMPLICIT_DEF
%4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
%5:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %4(s32)
G_STORE %5(s32), %6(p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
S_ENDPGM 0
...
---
name: icmp
body: |
bb.1:
liveins: $sgpr4_sgpr5
; CHECK-LABEL: MachineUniformityInfo for function: icmp
; CHECK-NEXT: ALL VALUES UNIFORM
%3:_(p4) = COPY $sgpr4_sgpr5
%13:_(s32) = G_CONSTANT i32 0
%7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
%8:_(s32) = G_LOAD %7(p4) :: (dereferenceable invariant load (s32), align 16, addrspace 4)
%9:_(s64) = G_CONSTANT i64 8
%10:_(p4) = G_PTR_ADD %7, %9(s64)
%11:_(p1) = G_LOAD %10(p4) :: (dereferenceable invariant load (p1), addrspace 4)
%12:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.icmp), %8(s32), %13(s32), 33
G_STORE %12(s64), %11(p1) :: (volatile store (s64) , addrspace 1)
S_ENDPGM 0
...
---
name: fcmp
body: |
bb.1:
liveins: $sgpr4_sgpr5
; CHECK-LABEL: MachineUniformityInfo for function: fcmp
; CHECK-NEXT: ALL VALUES UNIFORM
%3:_(p4) = COPY $sgpr4_sgpr5
%10:_(s32) = G_CONSTANT i32 0
%12:_(s32) = G_CONSTANT i32 1
%16:_(p1) = G_IMPLICIT_DEF
%7:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
%8:_(<2 x s32>) = G_LOAD %7(p4) :: (dereferenceable invariant load (<2 x s32>) , align 16, addrspace 4)
%9:_(s32) = G_EXTRACT_VECTOR_ELT %8(<2 x s32>), %10(s32)
%11:_(s32) = G_EXTRACT_VECTOR_ELT %8(<2 x s32>), %12(s32)
%13:_(s64) = G_CONSTANT i64 4
%14:_(p4) = G_PTR_ADD %7, %13(s64)
%15:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.fcmp), %9(s32), %11(s32), 33
G_STORE %15(s64), %16(p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
S_ENDPGM 0
...
---
name: ballot
body: |
bb.1:
liveins: $sgpr4_sgpr5
; CHECK-LABEL: MachineUniformityInfo for function: ballot
; CHECK-NEXT: ALL VALUES UNIFORM
%2:_(p4) = COPY $sgpr4_sgpr5
%10:_(p1) = G_IMPLICIT_DEF
%6:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
%7:_(s32) = G_LOAD %6(p4) :: (dereferenceable invariant load (s32), align 16, addrspace 4)
%8:_(s1) = G_TRUNC %7(s32)
%9:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.ballot), %8(s1)
G_STORE %9(s64), %10(p1) :: (volatile store (s64) into `i64 addrspace(1)* undef`, addrspace 1)
S_ENDPGM 0
...
---
name: asm_sgpr
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: sreg_32, preferred-register: '' }
- { id: 2, class: vgpr_32, preferred-register: '' }
- { id: 3, class: _, preferred-register: '' }
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: MachineUniformityInfo for function: asm_sgpr
; CHECK-NOT: DIVERGENT: %1
%0:_(s32) = COPY $vgpr0
%2:vgpr_32 = COPY %0(s32)
INLINEASM &"; def $0, $1", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1, 1835017 /* reguse:VGPR_32 */, %2
%3:_(s32) = COPY %1
$vgpr0 = COPY %3(s32)
SI_RETURN implicit $vgpr0
...
# FIXME :: BELOW INLINE ASM SHOULD BE DIVERGENT
---
name: asm_mixed_sgpr_vgpr
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: sreg_32, preferred-register: '' }
- { id: 2, class: vgpr_32, preferred-register: '' }
- { id: 3, class: vgpr_32, preferred-register: '' }
- { id: 4, class: _, preferred-register: '' }
- { id: 5, class: _, preferred-register: '' }
- { id: 6, class: _, preferred-register: '' }
liveins: []
frameInfo:
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: MachineUniformityInfo for function: asm_mixed_sgpr_vgpr
; CHECK: DIVERGENT: %0:
; CHECK: DIVERGENT: %3:
; CHECK: DIVERGENT: %2:
; CHECK: DIVERGENT: %5:
%0:_(s32) = COPY $vgpr0
%6:_(p1) = G_IMPLICIT_DEF
%3:vgpr_32 = COPY %0(s32)
INLINEASM &"; def $0, $1, $2", 0 /* attdialect */, 1966090 /* regdef:SReg_32 */, def %1, 1835018 /* regdef:VGPR_32 */, def %2, 1835017 /* reguse:VGPR_32 */, %3
%4:_(s32) = COPY %1
%5:_(s32) = COPY %2
G_STORE %5(s32), %6(p1) :: (store (s32) into `i32 addrspace(1)* undef`, addrspace 1)
SI_RETURN
...
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