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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s
---
name: zext_of_load_copy
alignment: 4
exposesReturnsTwice: false
legalized: true
regBankSelected: true
liveins:
- { reg: '$x0', virtual-reg: '' }
- { reg: '$x1', virtual-reg: '' }
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
bb.1:
liveins: $x0, $x1
; CHECK-LABEL: name: zext_of_load_copy
; CHECK: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load (s8))
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 4096
; CHECK-NEXT: $x0 = COPY [[ANDXri]]
%3:gpr(p0) = G_IMPLICIT_DEF
%2:gpr(s8) = G_LOAD %3(p0) :: (load (s8))
%4:gpr(s64) = G_ZEXT %2(s8)
%5:gpr(s64) = G_CONSTANT i64 1
%6:gpr(s64) = G_AND %4, %5
$x0 = COPY %6
...
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