1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -asm-verbose=1 < %s | FileCheck %s
;
; LD1SB/LD1B
;
define <vscale x 16 x i32> @ld1b_i8_sext_i32(<vscale x 16 x i8> *%base) {
; CHECK-LABEL: ld1b_i8_sext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0]
; CHECK-NEXT: ld1sb { z1.s }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ld1sb { z2.s }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1sb { z3.s }, p0/z, [x0, #3, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
%res = sext <vscale x 16 x i8> %wide.load to <vscale x 16 x i32>
ret <vscale x 16 x i32> %res
}
define <vscale x 16 x i32> @ld1b_i8_zext_i32(<vscale x 16 x i8> *%base) {
; CHECK-LABEL: ld1b_i8_zext_i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0]
; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ld1b { z2.s }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1b { z3.s }, p0/z, [x0, #3, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
%res = zext <vscale x 16 x i8> %wide.load to <vscale x 16 x i32>
ret <vscale x 16 x i32> %res
}
define <vscale x 16 x i64> @ld1b_i8_sext(<vscale x 16 x i8> *%base) {
; CHECK-LABEL: ld1b_i8_sext:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1sb { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1sb { z1.d }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ld1sb { z2.d }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1sb { z3.d }, p0/z, [x0, #3, mul vl]
; CHECK-NEXT: ld1sb { z4.d }, p0/z, [x0, #4, mul vl]
; CHECK-NEXT: ld1sb { z5.d }, p0/z, [x0, #5, mul vl]
; CHECK-NEXT: ld1sb { z6.d }, p0/z, [x0, #6, mul vl]
; CHECK-NEXT: ld1sb { z7.d }, p0/z, [x0, #7, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
%res = sext <vscale x 16 x i8> %wide.load to <vscale x 16 x i64>
ret <vscale x 16 x i64> %res
}
define <vscale x 16 x i64> @ld1b_i8_zext(<vscale x 16 x i8> *%base) {
; CHECK-LABEL: ld1b_i8_zext:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1b { z1.d }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ld1b { z2.d }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1b { z3.d }, p0/z, [x0, #3, mul vl]
; CHECK-NEXT: ld1b { z4.d }, p0/z, [x0, #4, mul vl]
; CHECK-NEXT: ld1b { z5.d }, p0/z, [x0, #5, mul vl]
; CHECK-NEXT: ld1b { z6.d }, p0/z, [x0, #6, mul vl]
; CHECK-NEXT: ld1b { z7.d }, p0/z, [x0, #7, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 16 x i8>, <vscale x 16 x i8>* %base
%res = zext <vscale x 16 x i8> %wide.load to <vscale x 16 x i64>
ret <vscale x 16 x i64> %res
}
;
; LD1H
;
define <vscale x 8 x i64> @ld1h_i16_sext(<vscale x 8 x i16> *%base) {
; CHECK-LABEL: ld1h_i16_sext:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1sh { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1sh { z1.d }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ld1sh { z2.d }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1sh { z3.d }, p0/z, [x0, #3, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 8 x i16>, <vscale x 8 x i16>* %base
%res = sext <vscale x 8 x i16> %wide.load to <vscale x 8 x i64>
ret <vscale x 8 x i64> %res
}
define <vscale x 8 x i64> @ld1h_i16_zext(<vscale x 8 x i16> *%base) {
; CHECK-LABEL: ld1h_i16_zext:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0, #2, mul vl]
; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, #3, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 8 x i16>, <vscale x 8 x i16>* %base
%res = zext <vscale x 8 x i16> %wide.load to <vscale x 8 x i64>
ret <vscale x 8 x i64> %res
}
;
; LD1W
;
define <vscale x 4 x i64> @ld1w_i32_sext(<vscale x 4 x i32> *%base) {
; CHECK-LABEL: ld1w_i32_sext:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1sw { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1sw { z1.d }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %base
%res = sext <vscale x 4 x i32> %wide.load to <vscale x 4 x i64>
ret <vscale x 4 x i64> %res
}
define <vscale x 4 x i64> @ld1w_i32_zext(<vscale x 4 x i32> *%base) {
; CHECK-LABEL: ld1w_i32_zext:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0, #1, mul vl]
; CHECK-NEXT: ret
%wide.load = load <vscale x 4 x i32>, <vscale x 4 x i32>* %base
%res = zext <vscale x 4 x i32> %wide.load to <vscale x 4 x i64>
ret <vscale x 4 x i64> %res
}
|
