1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch32 --filetype=obj --verify-machineinstrs < %s \
; RUN: -o /dev/null 2>&1
; RUN: llc --mtriple=loongarch64 --filetype=obj --verify-machineinstrs < %s \
; RUN: -o /dev/null 2>&1
; RUN: llc --mtriple=loongarch32 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA32
; RUN: llc --mtriple=loongarch64 --verify-machineinstrs < %s | FileCheck %s --check-prefix=LA64
define i32 @relax_b18(i32 signext %a, i32 signext %b) {
; LA32-LABEL: relax_b18:
; LA32: # %bb.0:
; LA32-NEXT: beq $a0, $a1, .LBB0_1
; LA32-NEXT: b .LBB0_2
; LA32-NEXT: .LBB0_1: # %iftrue
; LA32-NEXT: #APP
; LA32-NEXT: .space 1048576
; LA32-NEXT: #NO_APP
; LA32-NEXT: ori $a0, $zero, 1
; LA32-NEXT: ret
; LA32-NEXT: .LBB0_2: # %iffalse
; LA32-NEXT: move $a0, $zero
; LA32-NEXT: ret
;
; LA64-LABEL: relax_b18:
; LA64: # %bb.0:
; LA64-NEXT: beq $a0, $a1, .LBB0_1
; LA64-NEXT: b .LBB0_2
; LA64-NEXT: .LBB0_1: # %iftrue
; LA64-NEXT: #APP
; LA64-NEXT: .space 1048576
; LA64-NEXT: #NO_APP
; LA64-NEXT: ori $a0, $zero, 1
; LA64-NEXT: ret
; LA64-NEXT: .LBB0_2: # %iffalse
; LA64-NEXT: move $a0, $zero
; LA64-NEXT: ret
%cond = icmp eq i32 %a, %b
br i1 %cond, label %iftrue, label %iffalse
iftrue:
call void asm sideeffect ".space 1048576", ""()
ret i32 1
iffalse:
ret i32 0
}
define i32 @relax_b23(i1 %a) {
; LA32-LABEL: relax_b23:
; LA32: # %bb.0:
; LA32-NEXT: andi $a0, $a0, 1
; LA32-NEXT: bnez $a0, .LBB1_1
; LA32-NEXT: b .LBB1_2
; LA32-NEXT: .LBB1_1: # %iftrue
; LA32-NEXT: #APP
; LA32-NEXT: .space 16777216
; LA32-NEXT: #NO_APP
; LA32-NEXT: ori $a0, $zero, 1
; LA32-NEXT: ret
; LA32-NEXT: .LBB1_2: # %iffalse
; LA32-NEXT: move $a0, $zero
; LA32-NEXT: ret
;
; LA64-LABEL: relax_b23:
; LA64: # %bb.0:
; LA64-NEXT: andi $a0, $a0, 1
; LA64-NEXT: bnez $a0, .LBB1_1
; LA64-NEXT: b .LBB1_2
; LA64-NEXT: .LBB1_1: # %iftrue
; LA64-NEXT: #APP
; LA64-NEXT: .space 16777216
; LA64-NEXT: #NO_APP
; LA64-NEXT: ori $a0, $zero, 1
; LA64-NEXT: ret
; LA64-NEXT: .LBB1_2: # %iffalse
; LA64-NEXT: move $a0, $zero
; LA64-NEXT: ret
br i1 %a, label %iftrue, label %iffalse
iftrue:
call void asm sideeffect ".space 16777216", ""()
ret i32 1
iffalse:
ret i32 0
}
define i32 @relax_b28(i1 %a) {
; LA32-LABEL: relax_b28:
; LA32: # %bb.0:
; LA32-NEXT: addi.w $sp, $sp, -16
; LA32-NEXT: .cfi_def_cfa_offset 16
; LA32-NEXT: andi $a0, $a0, 1
; LA32-NEXT: bnez $a0, .LBB2_1
; LA32-NEXT: # %bb.3:
; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_2)
; LA32-NEXT: addi.w $a0, $a0, %pc_lo12(.LBB2_2)
; LA32-NEXT: jr $a0
; LA32-NEXT: .LBB2_1: # %iftrue
; LA32-NEXT: #APP
; LA32-NEXT: .space 536870912
; LA32-NEXT: #NO_APP
; LA32-NEXT: ori $a0, $zero, 1
; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: ret
; LA32-NEXT: .LBB2_2: # %iffalse
; LA32-NEXT: move $a0, $zero
; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: ret
;
; LA64-LABEL: relax_b28:
; LA64: # %bb.0:
; LA64-NEXT: addi.d $sp, $sp, -16
; LA64-NEXT: .cfi_def_cfa_offset 16
; LA64-NEXT: andi $a0, $a0, 1
; LA64-NEXT: bnez $a0, .LBB2_1
; LA64-NEXT: # %bb.3:
; LA64-NEXT: pcalau12i $a0, %pc_hi20(.LBB2_2)
; LA64-NEXT: addi.d $a0, $a0, %pc_lo12(.LBB2_2)
; LA64-NEXT: jr $a0
; LA64-NEXT: .LBB2_1: # %iftrue
; LA64-NEXT: #APP
; LA64-NEXT: .space 536870912
; LA64-NEXT: #NO_APP
; LA64-NEXT: ori $a0, $zero, 1
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
; LA64-NEXT: .LBB2_2: # %iffalse
; LA64-NEXT: move $a0, $zero
; LA64-NEXT: addi.d $sp, $sp, 16
; LA64-NEXT: ret
br i1 %a, label %iftrue, label %iffalse
iftrue:
call void asm sideeffect ".space 536870912", ""()
ret i32 1
iffalse:
ret i32 0
}
|
