1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s
define <2 x i16> @vwmaccus_vx_v2i16(ptr %x, i8 %y, <2 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i8>, ptr %x
%b = insertelement <2 x i8> poison, i8 %y, i32 0
%c = shufflevector <2 x i8> %b, <2 x i8> poison, <2 x i32> zeroinitializer
%d = sext <2 x i8> %a to <2 x i16>
%e = zext <2 x i8> %c to <2 x i16>
%f = mul <2 x i16> %d, %e
%g = add <2 x i16> %f, %z
ret <2 x i16> %g
}
define <4 x i16> @vwmaccus_vx_v4i16(ptr %x, i8 %y, <4 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <4 x i8>, ptr %x
%b = insertelement <4 x i8> poison, i8 %y, i32 0
%c = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> zeroinitializer
%d = sext <4 x i8> %a to <4 x i16>
%e = zext <4 x i8> %c to <4 x i16>
%f = mul <4 x i16> %d, %e
%g = add <4 x i16> %f, %z
ret <4 x i16> %g
}
define <2 x i32> @vwmaccus_vx_v2i32(ptr %x, i16 %y, <2 x i32> %z) {
; CHECK-LABEL: vwmaccus_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i16>, ptr %x
%b = insertelement <2 x i16> poison, i16 %y, i32 0
%c = shufflevector <2 x i16> %b, <2 x i16> poison, <2 x i32> zeroinitializer
%d = sext <2 x i16> %a to <2 x i32>
%e = zext <2 x i16> %c to <2 x i32>
%f = mul <2 x i32> %d, %e
%g = add <2 x i32> %f, %z
ret <2 x i32> %g
}
define <8 x i16> @vwmaccus_vx_v8i16(ptr %x, i8 %y, <8 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vle8.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <8 x i8>, ptr %x
%b = insertelement <8 x i8> poison, i8 %y, i32 0
%c = shufflevector <8 x i8> %b, <8 x i8> poison, <8 x i32> zeroinitializer
%d = sext <8 x i8> %a to <8 x i16>
%e = zext <8 x i8> %c to <8 x i16>
%f = mul <8 x i16> %d, %e
%g = add <8 x i16> %f, %z
ret <8 x i16> %g
}
define <4 x i32> @vwmaccus_vx_v4i32(ptr %x, i16 %y, <4 x i32> %z) {
; CHECK-LABEL: vwmaccus_vx_v4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <4 x i16>, ptr %x
%b = insertelement <4 x i16> poison, i16 %y, i32 0
%c = shufflevector <4 x i16> %b, <4 x i16> poison, <4 x i32> zeroinitializer
%d = sext <4 x i16> %a to <4 x i32>
%e = zext <4 x i16> %c to <4 x i32>
%f = mul <4 x i32> %d, %e
%g = add <4 x i32> %f, %z
ret <4 x i32> %g
}
define <2 x i64> @vwmaccus_vx_v2i64(ptr %x, i32 %y, <2 x i64> %z) {
; CHECK-LABEL: vwmaccus_vx_v2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vle32.v v9, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v9
; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = insertelement <2 x i32> poison, i32 %y, i64 0
%c = shufflevector <2 x i32> %b, <2 x i32> poison, <2 x i32> zeroinitializer
%d = sext <2 x i32> %a to <2 x i64>
%e = zext <2 x i32> %c to <2 x i64>
%f = mul <2 x i64> %d, %e
%g = add <2 x i64> %f, %z
ret <2 x i64> %g
}
define <16 x i16> @vwmaccus_vx_v16i16(ptr %x, i8 %y, <16 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vle8.v v10, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <16 x i8>, ptr %x
%b = insertelement <16 x i8> poison, i8 %y, i32 0
%c = shufflevector <16 x i8> %b, <16 x i8> poison, <16 x i32> zeroinitializer
%d = sext <16 x i8> %a to <16 x i16>
%e = zext <16 x i8> %c to <16 x i16>
%f = mul <16 x i16> %d, %e
%g = add <16 x i16> %f, %z
ret <16 x i16> %g
}
define <8 x i32> @vwmaccus_vx_v8i32(ptr %x, i16 %y, <8 x i32> %z) {
; CHECK-LABEL: vwmaccus_vx_v8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v10, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %x
%b = insertelement <8 x i16> poison, i16 %y, i32 0
%c = shufflevector <8 x i16> %b, <8 x i16> poison, <8 x i32> zeroinitializer
%d = sext <8 x i16> %a to <8 x i32>
%e = zext <8 x i16> %c to <8 x i32>
%f = mul <8 x i32> %d, %e
%g = add <8 x i32> %f, %z
ret <8 x i32> %g
}
define <4 x i64> @vwmaccus_vx_v4i64(ptr %x, i32 %y, <4 x i64> %z) {
; CHECK-LABEL: vwmaccus_vx_v4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vle32.v v10, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v10
; CHECK-NEXT: ret
%a = load <4 x i32>, ptr %x
%b = insertelement <4 x i32> poison, i32 %y, i64 0
%c = shufflevector <4 x i32> %b, <4 x i32> poison, <4 x i32> zeroinitializer
%d = sext <4 x i32> %a to <4 x i64>
%e = zext <4 x i32> %c to <4 x i64>
%f = mul <4 x i64> %d, %e
%g = add <4 x i64> %f, %z
ret <4 x i64> %g
}
define <32 x i16> @vwmaccus_vx_v32i16(ptr %x, i8 %y, <32 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e8, m2, ta, ma
; CHECK-NEXT: vle8.v v12, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <32 x i8>, ptr %x
%b = insertelement <32 x i8> poison, i8 %y, i32 0
%c = shufflevector <32 x i8> %b, <32 x i8> poison, <32 x i32> zeroinitializer
%d = sext <32 x i8> %a to <32 x i16>
%e = zext <32 x i8> %c to <32 x i16>
%f = mul <32 x i16> %d, %e
%g = add <32 x i16> %f, %z
ret <32 x i16> %g
}
define <16 x i32> @vwmaccus_vx_v16i32(ptr %x, i16 %y, <16 x i32> %z) {
; CHECK-LABEL: vwmaccus_vx_v16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vle16.v v12, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <16 x i16>, ptr %x
%b = insertelement <16 x i16> poison, i16 %y, i32 0
%c = shufflevector <16 x i16> %b, <16 x i16> poison, <16 x i32> zeroinitializer
%d = sext <16 x i16> %a to <16 x i32>
%e = zext <16 x i16> %c to <16 x i32>
%f = mul <16 x i32> %d, %e
%g = add <16 x i32> %f, %z
ret <16 x i32> %g
}
define <8 x i64> @vwmaccus_vx_v8i64(ptr %x, i32 %y, <8 x i64> %z) {
; CHECK-LABEL: vwmaccus_vx_v8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; CHECK-NEXT: vle32.v v12, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v12
; CHECK-NEXT: ret
%a = load <8 x i32>, ptr %x
%b = insertelement <8 x i32> poison, i32 %y, i64 0
%c = shufflevector <8 x i32> %b, <8 x i32> poison, <8 x i32> zeroinitializer
%d = sext <8 x i32> %a to <8 x i64>
%e = zext <8 x i32> %c to <8 x i64>
%f = mul <8 x i64> %d, %e
%g = add <8 x i64> %f, %z
ret <8 x i64> %g
}
define <64 x i16> @vwmaccus_vx_v64i16(ptr %x, i8 %y, <64 x i16> %z) {
; CHECK-LABEL: vwmaccus_vx_v64i16:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 64
; CHECK-NEXT: vsetvli zero, a2, e8, m4, ta, ma
; CHECK-NEXT: vle8.v v16, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <64 x i8>, ptr %x
%b = insertelement <64 x i8> poison, i8 %y, i32 0
%c = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer
%d = sext <64 x i8> %a to <64 x i16>
%e = zext <64 x i8> %c to <64 x i16>
%f = mul <64 x i16> %d, %e
%g = add <64 x i16> %f, %z
ret <64 x i16> %g
}
define <32 x i32> @vwmaccus_vx_v32i32(ptr %x, i16 %y, <32 x i32> %z) {
; CHECK-LABEL: vwmaccus_vx_v32i32:
; CHECK: # %bb.0:
; CHECK-NEXT: li a2, 32
; CHECK-NEXT: vsetvli zero, a2, e16, m4, ta, ma
; CHECK-NEXT: vle16.v v16, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <32 x i16>, ptr %x
%b = insertelement <32 x i16> poison, i16 %y, i32 0
%c = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer
%d = sext <32 x i16> %a to <32 x i32>
%e = zext <32 x i16> %c to <32 x i32>
%f = mul <32 x i32> %d, %e
%g = add <32 x i32> %f, %z
ret <32 x i32> %g
}
define <16 x i64> @vwmaccus_vx_v16i64(ptr %x, i32 %y, <16 x i64> %z) {
; CHECK-LABEL: vwmaccus_vx_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vle32.v v16, (a0)
; CHECK-NEXT: vwmaccus.vx v8, a1, v16
; CHECK-NEXT: ret
%a = load <16 x i32>, ptr %x
%b = insertelement <16 x i32> poison, i32 %y, i64 0
%c = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer
%d = sext <16 x i32> %a to <16 x i64>
%e = zext <16 x i32> %c to <16 x i64>
%f = mul <16 x i64> %d, %e
%g = add <16 x i64> %f, %z
ret <16 x i64> %g
}
|
