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|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=armv8.1m.main -mattr=+lob -run-pass=arm-low-overhead-loops --verify-machineinstrs %s -o - | FileCheck %s
--- |
define void @size_limit(ptr nocapture %a, ptr nocapture readonly %b, ptr nocapture readonly %c, i32 %N) {
entry:
%cmp8 = icmp eq i32 %N, 0
br i1 %cmp8, label %for.cond.cleanup, label %for.body.preheader
for.body.preheader: ; preds = %entry
%start = call i32 @llvm.start.loop.iterations.i32(i32 %N)
br label %for.body
for.cond.cleanup: ; preds = %for.end, %entry
ret void
for.body: ; preds = %for.end, %for.body.preheader
%lsr.iv4 = phi ptr [ %b, %for.body.preheader ], [ %scevgep5, %for.end ]
%lsr.iv2 = phi ptr [ %c, %for.body.preheader ], [ %scevgep3, %for.end ]
%lsr.iv1 = phi ptr [ %a, %for.body.preheader ], [ %scevgep, %for.end ]
%lsr.iv = phi i32 [ %start, %for.body.preheader ], [ %lsr.iv.next, %for.end ]
%size = call i32 @llvm.arm.space(i32 3072, i32 undef)
%0 = load i32, ptr %lsr.iv4, align 4
%1 = load i32, ptr %lsr.iv2, align 4
%mul = mul nsw i32 %1, %0
store i32 %mul, ptr %lsr.iv1, align 4
%cmp = icmp ne i32 %0, 0
br i1 %cmp, label %middle.block, label %for.end
middle.block: ; preds = %for.body
%div = udiv i32 %1, %0
store i32 %div, ptr %lsr.iv1, align 4
%size.1 = call i32 @llvm.arm.space(i32 1024, i32 undef)
br label %for.end
for.end: ; preds = %middle.block, %for.body
%scevgep = getelementptr i32, ptr %lsr.iv1, i32 1
%scevgep3 = getelementptr i32, ptr %lsr.iv2, i32 1
%scevgep5 = getelementptr i32, ptr %lsr.iv4, i32 1
%lsr.iv.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv, i32 1)
%exitcond = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond, label %for.cond.cleanup, label %for.body
}
; Function Attrs: nounwind
declare i32 @llvm.arm.space(i32 immarg, i32) #0
; Function Attrs: noduplicate nounwind
declare i32 @llvm.start.loop.iterations.i32(i32) #1
; Function Attrs: noduplicate nounwind
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
; Function Attrs: nounwind
declare void @llvm.stackprotector(ptr, ptr) #0
attributes #0 = { nounwind }
attributes #1 = { noduplicate nounwind }
...
---
name: size_limit
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 8
offsetAdjustment: 0
maxAlignment: 4
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: size_limit
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -8
; CHECK: tCMPi8 $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2IT 0, 8, implicit-def $itstate
; CHECK: tPOP_RET 0 /* CC::eq */, killed $cpsr, def $r4, def $pc, implicit killed $itstate
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: dead $lr = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: tB %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.2.for.end:
; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $lr = t2SUBri killed renamable $lr, 1, 14 /* CC::al */, $noreg, def $cpsr
; CHECK: tBcc %bb.3, 1 /* CC::ne */, killed $cpsr
; CHECK: t2B %bb.5, 14 /* CC::al */, $noreg
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.4(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $lr, $r0, $r1, $r2
; CHECK: dead renamable $r3 = SPACE 3072, undef renamable $r0
; CHECK: renamable $r3 = tLDRi renamable $r1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv4)
; CHECK: renamable $r12 = t2LDRi12 renamable $r2, 0, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv2)
; CHECK: tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r4, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1)
; CHECK: t2Bcc %bb.2, 0 /* CC::eq */, killed $cpsr
; CHECK: bb.4.middle.block:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
; CHECK: renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14 /* CC::al */, $noreg
; CHECK: tSTRi killed renamable $r3, renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.lsr.iv1)
; CHECK: dead renamable $r3 = SPACE 1024, undef renamable $r0
; CHECK: t2B %bb.2, 14 /* CC::al */, $noreg
; CHECK: bb.5.for.cond.cleanup:
; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
bb.0.entry:
successors: %bb.1(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr
frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
frame-setup CFI_INSTRUCTION def_cfa_offset 8
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r4, -8
tCMPi8 $r3, 0, 14, $noreg, implicit-def $cpsr
t2IT 0, 8, implicit-def $itstate
tPOP_RET 0, killed $cpsr, def $r4, def $pc, implicit killed $itstate
bb.1.for.body.preheader:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3, $r4, $lr
$lr = tMOVr $r3, 14, $noreg
$lr = t2DoLoopStart killed $r3
tB %bb.2, 14, $noreg
bb.2.for.end:
successors: %bb.5(0x04000000), %bb.3(0x7c000000)
liveins: $lr, $r0, $r1, $r2
renamable $r1, dead $cpsr = tADDi8 killed renamable $r1, 4, 14, $noreg
renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 4, 14, $noreg
renamable $r0, dead $cpsr = tADDi8 killed renamable $r0, 4, 14, $noreg
renamable $lr = t2LoopDec killed renamable $lr, 1
t2LoopEnd renamable $lr, %bb.3, implicit-def dead $cpsr
t2B %bb.5, 14, $noreg
bb.3.for.body:
successors: %bb.4(0x50000000), %bb.2(0x30000000)
liveins: $lr, $r0, $r1, $r2
dead renamable $r3 = SPACE 3072, undef renamable $r0
renamable $r3 = tLDRi renamable $r1, 0, 14, $noreg :: (load (s32) from %ir.lsr.iv4)
renamable $r12 = t2LDRi12 renamable $r2, 0, 14, $noreg :: (load (s32) from %ir.lsr.iv2)
tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
renamable $r4 = nsw t2MUL renamable $r12, renamable $r3, 14, $noreg
tSTRi killed renamable $r4, renamable $r0, 0, 14, $noreg :: (store (s32) into %ir.lsr.iv1)
t2Bcc %bb.2, 0, killed $cpsr
bb.4.middle.block:
successors: %bb.2(0x80000000)
liveins: $lr, $r0, $r1, $r2, $r3, $r12
renamable $r3 = t2UDIV killed renamable $r12, killed renamable $r3, 14, $noreg
tSTRi killed renamable $r3, renamable $r0, 0, 14, $noreg :: (store (s32) into %ir.lsr.iv1)
dead renamable $r3 = SPACE 1024, undef renamable $r0
t2B %bb.2, 14, $noreg
bb.5.for.cond.cleanup:
tPOP_RET 14, $noreg, def $r4, def $pc
...
|
