File: unrolled-and-vector.mir

package info (click to toggle)
llvm-toolchain-16 1%3A16.0.6-15~deb12u1
  • links: PTS, VCS
  • area: main
  • in suites: bookworm
  • size: 1,634,792 kB
  • sloc: cpp: 6,179,261; ansic: 1,216,205; asm: 741,319; python: 196,614; objc: 75,325; f90: 49,640; lisp: 32,396; pascal: 12,286; sh: 9,394; perl: 7,442; ml: 5,494; awk: 3,523; makefile: 2,723; javascript: 1,206; xml: 886; fortran: 581; cs: 573
file content (532 lines) | stat: -rw-r--r-- 31,346 bytes parent folder | download | duplicates (9)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s

--- |
  define dso_local arm_aapcs_vfpcc void @unrolled_and_vector(i8* nocapture %res, i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
  entry:
    %cmp10 = icmp eq i32 %N, 0
    br i1 %cmp10, label %for.cond.cleanup, label %vector.memcheck

  vector.memcheck:                                  ; preds = %entry
    %scevgep = getelementptr i8, i8* %res, i32 %N
    %scevgep12 = getelementptr i8, i8* %a, i32 %N
    %scevgep13 = getelementptr i8, i8* %b, i32 %N
    %bound0 = icmp ugt i8* %scevgep12, %res
    %bound1 = icmp ugt i8* %scevgep, %a
    %found.conflict = and i1 %bound0, %bound1
    %bound014 = icmp ugt i8* %scevgep13, %res
    %bound115 = icmp ugt i8* %scevgep, %b
    %found.conflict16 = and i1 %bound014, %bound115
    %conflict.rdx = or i1 %found.conflict, %found.conflict16
    %0 = add i32 %N, 15
    %1 = lshr i32 %0, 4
    %2 = shl nuw i32 %1, 4
    %3 = add i32 %2, -16
    %4 = lshr i32 %3, 4
    %5 = add nuw nsw i32 %4, 1
    br i1 %conflict.rdx, label %for.body.preheader, label %vector.ph

  for.body.preheader:                               ; preds = %vector.memcheck
    %6 = add i32 %N, -1
    %xtraiter = and i32 %N, 3
    %7 = icmp ult i32 %6, 3
    %8 = add i32 %N, -4
    %9 = sub i32 %8, %xtraiter
    %10 = lshr i32 %9, 2
    %11 = add nuw nsw i32 %10, 1
    br i1 %7, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new

  for.body.preheader.new:                           ; preds = %for.body.preheader
    %start1 = call i32 @llvm.start.loop.iterations.i32(i32 %11)
    br label %for.body

  vector.ph:                                        ; preds = %vector.memcheck
    %start2 = call i32 @llvm.start.loop.iterations.i32(i32 %5)
    br label %vector.body

  vector.body:                                      ; preds = %vector.body, %vector.ph
    %lsr.iv50 = phi i8* [ %scevgep51, %vector.body ], [ %res, %vector.ph ]
    %lsr.iv47 = phi i8* [ %scevgep48, %vector.body ], [ %b, %vector.ph ]
    %lsr.iv = phi i8* [ %scevgep45, %vector.body ], [ %a, %vector.ph ]
    %12 = phi i32 [ %start2, %vector.ph ], [ %17, %vector.body ]
    %13 = phi i32 [ %N, %vector.ph ], [ %15, %vector.body ]
    %lsr.iv5052 = bitcast i8* %lsr.iv50 to <16 x i8>*
    %lsr.iv4749 = bitcast i8* %lsr.iv47 to <16 x i8>*
    %lsr.iv46 = bitcast i8* %lsr.iv to <16 x i8>*
    %14 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %13)
    %15 = sub i32 %13, 16
    %wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv46, i32 1, <16 x i1> %14, <16 x i8> undef)
    %wide.masked.load19 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv4749, i32 1, <16 x i1> %14, <16 x i8> undef)
    %16 = add <16 x i8> %wide.masked.load19, %wide.masked.load
    call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %16, <16 x i8>* %lsr.iv5052, i32 1, <16 x i1> %14)
    %scevgep45 = getelementptr i8, i8* %lsr.iv, i32 16
    %scevgep48 = getelementptr i8, i8* %lsr.iv47, i32 16
    %scevgep51 = getelementptr i8, i8* %lsr.iv50, i32 16
    %17 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %12, i32 1)
    %18 = icmp ne i32 %17, 0
    br i1 %18, label %vector.body, label %for.cond.cleanup

  for.cond.cleanup.loopexit.unr-lcssa:              ; preds = %for.body, %for.body.preheader
    %i.011.unr = phi i32 [ 0, %for.body.preheader ], [ %inc.3, %for.body ]
    %lcmp.mod = icmp eq i32 %xtraiter, 0
    br i1 %lcmp.mod, label %for.cond.cleanup, label %for.body.epil

  for.body.epil:                                    ; preds = %for.cond.cleanup.loopexit.unr-lcssa
    %arrayidx.epil = getelementptr inbounds i8, i8* %a, i32 %i.011.unr
    %19 = load i8, i8* %arrayidx.epil, align 1
    %arrayidx1.epil = getelementptr inbounds i8, i8* %b, i32 %i.011.unr
    %20 = load i8, i8* %arrayidx1.epil, align 1
    %add.epil = add i8 %20, %19
    %arrayidx4.epil = getelementptr inbounds i8, i8* %res, i32 %i.011.unr
    store i8 %add.epil, i8* %arrayidx4.epil, align 1
    %inc.epil = add nuw i32 %i.011.unr, 1
    %epil.iter.cmp = icmp eq i32 %xtraiter, 1
    br i1 %epil.iter.cmp, label %for.cond.cleanup, label %for.body.epil.1

  for.cond.cleanup:                                 ; preds = %vector.body, %for.cond.cleanup.loopexit.unr-lcssa, %for.body.epil.1, %for.body.epil, %for.body.epil.2, %entry
    ret void

  for.body:                                         ; preds = %for.body, %for.body.preheader.new
    %i.011 = phi i32 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
    %21 = phi i32 [ %start1, %for.body.preheader.new ], [ %30, %for.body ]
    %scevgep23 = getelementptr i8, i8* %a, i32 %i.011
    %scevgep2453 = bitcast i8* %scevgep23 to i8*
    %22 = load i8, i8* %scevgep2453, align 1
    %scevgep27 = getelementptr i8, i8* %b, i32 %i.011
    %scevgep2854 = bitcast i8* %scevgep27 to i8*
    %23 = load i8, i8* %scevgep2854, align 1
    %add = add i8 %23, %22
    %scevgep31 = getelementptr i8, i8* %res, i32 %i.011
    %scevgep3255 = bitcast i8* %scevgep31 to i8*
    store i8 %add, i8* %scevgep3255, align 1
    %scevgep39 = getelementptr i8, i8* %a, i32 %i.011
    %scevgep40 = getelementptr i8, i8* %scevgep39, i32 1
    %24 = load i8, i8* %scevgep40, align 1
    %scevgep41 = getelementptr i8, i8* %b, i32 %i.011
    %scevgep42 = getelementptr i8, i8* %scevgep41, i32 1
    %25 = load i8, i8* %scevgep42, align 1
    %add.1 = add i8 %25, %24
    %scevgep43 = getelementptr i8, i8* %res, i32 %i.011
    %scevgep44 = getelementptr i8, i8* %scevgep43, i32 1
    store i8 %add.1, i8* %scevgep44, align 1
    %scevgep33 = getelementptr i8, i8* %a, i32 %i.011
    %scevgep34 = getelementptr i8, i8* %scevgep33, i32 2
    %26 = load i8, i8* %scevgep34, align 1
    %scevgep35 = getelementptr i8, i8* %b, i32 %i.011
    %scevgep36 = getelementptr i8, i8* %scevgep35, i32 2
    %27 = load i8, i8* %scevgep36, align 1
    %add.2 = add i8 %27, %26
    %scevgep37 = getelementptr i8, i8* %res, i32 %i.011
    %scevgep38 = getelementptr i8, i8* %scevgep37, i32 2
    store i8 %add.2, i8* %scevgep38, align 1
    %scevgep21 = getelementptr i8, i8* %a, i32 %i.011
    %scevgep22 = getelementptr i8, i8* %scevgep21, i32 3
    %28 = load i8, i8* %scevgep22, align 1
    %scevgep25 = getelementptr i8, i8* %b, i32 %i.011
    %scevgep26 = getelementptr i8, i8* %scevgep25, i32 3
    %29 = load i8, i8* %scevgep26, align 1
    %add.3 = add i8 %29, %28
    %scevgep29 = getelementptr i8, i8* %res, i32 %i.011
    %scevgep30 = getelementptr i8, i8* %scevgep29, i32 3
    store i8 %add.3, i8* %scevgep30, align 1
    %inc.3 = add nuw i32 %i.011, 4
    %30 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1)
    %31 = icmp ne i32 %30, 0
    br i1 %31, label %for.body, label %for.cond.cleanup.loopexit.unr-lcssa

  for.body.epil.1:                                  ; preds = %for.body.epil
    %arrayidx.epil.1 = getelementptr inbounds i8, i8* %a, i32 %inc.epil
    %32 = load i8, i8* %arrayidx.epil.1, align 1
    %arrayidx1.epil.1 = getelementptr inbounds i8, i8* %b, i32 %inc.epil
    %33 = load i8, i8* %arrayidx1.epil.1, align 1
    %add.epil.1 = add i8 %33, %32
    %arrayidx4.epil.1 = getelementptr inbounds i8, i8* %res, i32 %inc.epil
    store i8 %add.epil.1, i8* %arrayidx4.epil.1, align 1
    %inc.epil.1 = add nuw i32 %i.011.unr, 2
    %epil.iter.cmp.1 = icmp eq i32 %xtraiter, 2
    br i1 %epil.iter.cmp.1, label %for.cond.cleanup, label %for.body.epil.2

  for.body.epil.2:                                  ; preds = %for.body.epil.1
    %arrayidx.epil.2 = getelementptr inbounds i8, i8* %a, i32 %inc.epil.1
    %34 = load i8, i8* %arrayidx.epil.2, align 1
    %arrayidx1.epil.2 = getelementptr inbounds i8, i8* %b, i32 %inc.epil.1
    %35 = load i8, i8* %arrayidx1.epil.2, align 1
    %add.epil.2 = add i8 %35, %34
    %arrayidx4.epil.2 = getelementptr inbounds i8, i8* %res, i32 %inc.epil.1
    store i8 %add.epil.2, i8* %arrayidx4.epil.2, align 1
    br label %for.cond.cleanup
  }

  declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) #1
  declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>) #2
  declare i32 @llvm.start.loop.iterations.i32(i32) #3
  declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
  declare <16 x i1> @llvm.arm.mve.vctp8(i32) #4

...
---
name:            unrolled_and_vector
alignment:       2
exposesReturnsTwice: false
legalized:       false
regBankSelected: false
selected:        false
failedISel:      false
tracksRegLiveness: true
hasWinCFI:       false
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
  - { reg: '$r2', virtual-reg: '' }
  - { reg: '$r3', virtual-reg: '' }
frameInfo:
  isFrameAddressTaken: false
  isReturnAddressTaken: false
  hasStackMap:     false
  hasPatchPoint:   false
  stackSize:       32
  offsetAdjustment: -24
  maxAlignment:    4
  adjustsStack:    false
  hasCalls:        false
  stackProtector:  ''
  maxCallFrameSize: 0
  cvBytesOfCalleeSavedRegisters: 0
  hasOpaqueSPAdjustment: false
  hasVAStart:      false
  hasMustTailInVarArgFunc: false
  localFrameSize:  0
  savePoint:       ''
  restorePoint:    ''
fixedStack:      []
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites:       []
constants:       []
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: unrolled_and_vector
  ; CHECK: bb.0.entry:
  ; CHECK:   successors: %bb.11(0x30000000), %bb.1(0x50000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11
  ; CHECK:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa_offset 20
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r6, -12
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r5, -16
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r4, -20
  ; CHECK:   dead $r7 = frame-setup tADDrSPi $sp, 3, 14 /* CC::al */, $noreg
  ; CHECK:   frame-setup CFI_INSTRUCTION def_cfa $r7, 8
  ; CHECK:   $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r8, killed $r9, killed $r11
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r11, -24
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r9, -28
  ; CHECK:   frame-setup CFI_INSTRUCTION offset $r8, -32
  ; CHECK:   tCMPi8 renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
  ; CHECK: bb.1.vector.memcheck:
  ; CHECK:   successors: %bb.2(0x40000000), %bb.4(0x40000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
  ; CHECK:   tCMPr renamable $r4, renamable $r2, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $lr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
  ; CHECK:   tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
  ; CHECK:   tCMPr killed renamable $r4, renamable $r1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
  ; CHECK:   tCMPr killed renamable $r5, renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
  ; CHECK:   renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
  ; CHECK:   dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14 /* CC::al */, $noreg
  ; CHECK:   t2IT 0, 4, implicit-def $itstate
  ; CHECK:   renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0 /* CC::eq */, $cpsr, $noreg, implicit killed $r6, implicit $itstate
  ; CHECK:   dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0 /* CC::eq */, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
  ; CHECK:   tBcc %bb.4, 0 /* CC::eq */, killed $cpsr
  ; CHECK: bb.2.for.body.preheader:
  ; CHECK:   successors: %bb.3(0x40000000), %bb.6(0x40000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3
  ; CHECK:   renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r12 = t2ANDri renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   tCMPi8 killed renamable $r4, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.6, 2 /* CC::hs */, killed $cpsr
  ; CHECK: bb.3:
  ; CHECK:   successors: %bb.8(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r12
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
  ; CHECK:   tB %bb.8, 14 /* CC::al */, $noreg
  ; CHECK: bb.4.vector.ph:
  ; CHECK:   successors: %bb.5(0x80000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   $lr = MVE_DLSTP_8 killed renamable $r3
  ; CHECK: bb.5.vector.body:
  ; CHECK:   successors: %bb.5(0x7c000000), %bb.11(0x04000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2
  ; CHECK:   renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv46, align 1)
  ; CHECK:   renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1)
  ; CHECK:   renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK:   renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1)
  ; CHECK:   $lr = MVE_LETP killed renamable $lr, %bb.5
  ; CHECK:   tB %bb.11, 14 /* CC::al */, $noreg
  ; CHECK: bb.6.for.body.preheader.new:
  ; CHECK:   successors: %bb.7(0x80000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
  ; CHECK:   renamable $r3 = t2BICri killed renamable $r3, 3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
  ; CHECK: bb.7.for.body:
  ; CHECK:   successors: %bb.7(0x7c000000), %bb.8(0x04000000)
  ; CHECK:   liveins: $lr, $r0, $r1, $r2, $r3, $r12
  ; CHECK:   renamable $r4 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2453)
  ; CHECK:   renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14 /* CC::al */, $noreg, $noreg
  ; CHECK:   renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep2854)
  ; CHECK:   renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRBr killed renamable $r4, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep3255)
  ; CHECK:   renamable $r8 = t2LDRBi12 renamable $r9, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep40)
  ; CHECK:   renamable $r5 = tLDRBi renamable $r6, 1, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep42)
  ; CHECK:   renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14 /* CC::al */, $noreg
  ; CHECK:   t2STRBi12 killed renamable $r8, renamable $r5, 1, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep44)
  ; CHECK:   renamable $r8 = t2LDRBi12 renamable $r9, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep34)
  ; CHECK:   renamable $r4 = tLDRBi renamable $r6, 2, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep36)
  ; CHECK:   renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRBi killed renamable $r4, renamable $r5, 2, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep38)
  ; CHECK:   renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep22)
  ; CHECK:   renamable $r6 = tLDRBi killed renamable $r6, 3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.scevgep26)
  ; CHECK:   renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRBi killed renamable $r4, killed renamable $r5, 3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.scevgep30)
  ; CHECK:   $lr = t2LEUpdate killed renamable $lr, %bb.7
  ; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa:
  ; CHECK:   successors: %bb.11(0x30000000), %bb.9(0x50000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r12
  ; CHECK:   t2CMPri renamable $r12, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
  ; CHECK: bb.9.for.body.epil:
  ; CHECK:   successors: %bb.11(0x40000000), %bb.10(0x40000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r12
  ; CHECK:   renamable $r6 = tLDRBr renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil)
  ; CHECK:   t2CMPri renamable $r12, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $r5 = tLDRBr renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil)
  ; CHECK:   renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRBr killed renamable $r6, renamable $r0, $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil)
  ; CHECK:   tBcc %bb.11, 0 /* CC::eq */, killed $cpsr
  ; CHECK: bb.10.for.body.epil.1:
  ; CHECK:   successors: %bb.11(0x40000000), %bb.12(0x40000000)
  ; CHECK:   liveins: $r0, $r1, $r2, $r3, $r12
  ; CHECK:   renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14 /* CC::al */, $noreg
  ; CHECK:   t2CMPri killed renamable $r12, 2, 14 /* CC::al */, $noreg, implicit-def $cpsr
  ; CHECK:   renamable $r5 = tLDRBr renamable $r1, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.1)
  ; CHECK:   renamable $r4 = tLDRBr renamable $r2, $r6, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.1)
  ; CHECK:   renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.1)
  ; CHECK:   tBcc %bb.12, 1 /* CC::ne */, killed $cpsr
  ; CHECK: bb.11.for.cond.cleanup:
  ; CHECK:   $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
  ; CHECK: bb.12.for.body.epil.2:
  ; CHECK:   liveins: $r0, $r1, $r2, $r3
  ; CHECK:   renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14 /* CC::al */, $noreg
  ; CHECK:   renamable $r1 = tLDRBr killed renamable $r1, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx.epil.2)
  ; CHECK:   renamable $r2 = tLDRBr killed renamable $r2, $r3, 14 /* CC::al */, $noreg :: (load (s8) from %ir.arrayidx1.epil.2)
  ; CHECK:   renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
  ; CHECK:   tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14 /* CC::al */, $noreg :: (store (s8) into %ir.arrayidx4.epil.2)
  ; CHECK:   $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r8, def $r9, def $r11
  ; CHECK:   tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
  bb.0.entry:
    successors: %bb.11(0x30000000), %bb.1(0x50000000)
    liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11

    frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 20
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    frame-setup CFI_INSTRUCTION offset $r6, -12
    frame-setup CFI_INSTRUCTION offset $r5, -16
    frame-setup CFI_INSTRUCTION offset $r4, -20
    $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
    frame-setup CFI_INSTRUCTION def_cfa $r7, 8
    $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r11
    frame-setup CFI_INSTRUCTION offset $r11, -24
    frame-setup CFI_INSTRUCTION offset $r9, -28
    frame-setup CFI_INSTRUCTION offset $r8, -32
    tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
    tBcc %bb.11, 0, killed $cpsr

  bb.1.vector.memcheck:
    successors: %bb.2(0x40000000), %bb.4(0x40000000)
    liveins: $r0, $r1, $r2, $r3

    renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg
    renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
    tCMPr renamable $r4, renamable $r2, 14, $noreg, implicit-def $cpsr
    renamable $lr = t2MOVi 1, 14, $noreg, $noreg
    renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
    tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr
    renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
    tCMPr killed renamable $r4, renamable $r1, 14, $noreg, implicit-def $cpsr
    renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg
    renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
    tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr
    renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
    renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14, $noreg
    dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14, $noreg
    t2IT 0, 4, implicit-def $itstate
    renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0, $cpsr, $noreg, implicit $r6, implicit $itstate
    dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
    tBcc %bb.4, 0, killed $cpsr

  bb.2.for.body.preheader:
    successors: %bb.3(0x40000000), %bb.6(0x40000000)
    liveins: $lr, $r0, $r1, $r2, $r3

    renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg
    renamable $r12 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg
    tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr
    tBcc %bb.6, 2, killed $cpsr

  bb.3:
    successors: %bb.8(0x80000000)
    liveins: $r0, $r1, $r2, $r12

    renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
    tB %bb.8, 14, $noreg

  bb.4.vector.ph:
    successors: %bb.5(0x80000000)
    liveins: $lr, $r0, $r1, $r2, $r3

    renamable $r6 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg
    renamable $r6 = t2BICri killed renamable $r6, 15, 14, $noreg, $noreg
    renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 16, 14, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r6, 35, 14, $noreg, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.5.vector.body:
    successors: %bb.5(0x7c000000), %bb.11(0x04000000)
    liveins: $lr, $r0, $r1, $r2, $r3

    renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
    MVE_VPST 4, implicit $vpr
    renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv46, align 1)
    renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr, $noreg :: (load (s128) from %ir.lsr.iv4749, align 1)
    renamable $lr = t2LoopDec killed renamable $lr, 1
    renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, $noreg, undef renamable $q0
    MVE_VPST 8, implicit $vpr
    renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr, $noreg :: (store (s128) into %ir.lsr.iv5052, align 1)
    t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
    tB %bb.11, 14, $noreg

  bb.6.for.body.preheader.new:
    successors: %bb.7(0x80000000)
    liveins: $lr, $r0, $r1, $r2, $r3, $r12

    renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
    renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
    renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14, $noreg, $noreg
    renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
    $lr = t2DoLoopStart renamable $lr

  bb.7.for.body:
    successors: %bb.7(0x7c000000), %bb.8(0x04000000)
    liveins: $lr, $r0, $r1, $r2, $r3, $r12

    renamable $r4 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load (s8) from %ir.scevgep2453)
    renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg
    renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load (s8) from %ir.scevgep2854)
    renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
    renamable $lr = t2LoopDec killed renamable $lr, 1
    renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14, $noreg
    tSTRBr killed renamable $r4, renamable $r0, $r3, 14, $noreg :: (store (s8) into %ir.scevgep3255)
    renamable $r8 = t2LDRBi12 renamable $r9, 1, 14, $noreg :: (load (s8) from %ir.scevgep40)
    renamable $r5 = tLDRBi renamable $r6, 1, 14, $noreg :: (load (s8) from %ir.scevgep42)
    renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14, $noreg
    renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg
    renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg
    t2STRBi12 killed renamable $r8, renamable $r5, 1, 14, $noreg :: (store (s8) into %ir.scevgep44)
    renamable $r8 = t2LDRBi12 renamable $r9, 2, 14, $noreg :: (load (s8) from %ir.scevgep34)
    renamable $r4 = tLDRBi renamable $r6, 2, 14, $noreg :: (load (s8) from %ir.scevgep36)
    renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14, $noreg
    tSTRBi killed renamable $r4, renamable $r5, 2, 14, $noreg :: (store (s8) into %ir.scevgep38)
    renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14, $noreg :: (load (s8) from %ir.scevgep22)
    renamable $r6 = tLDRBi killed renamable $r6, 3, 14, $noreg :: (load (s8) from %ir.scevgep26)
    renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14, $noreg
    tSTRBi killed renamable $r4, killed renamable $r5, 3, 14, $noreg :: (store (s8) into %ir.scevgep30)
    t2LoopEnd renamable $lr, %bb.7, implicit-def dead $cpsr
    tB %bb.8, 14, $noreg

  bb.8.for.cond.cleanup.loopexit.unr-lcssa:
    successors: %bb.11(0x30000000), %bb.9(0x50000000)
    liveins: $r0, $r1, $r2, $r3, $r12

    t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr
    tBcc %bb.11, 0, killed $cpsr

  bb.9.for.body.epil:
    successors: %bb.11(0x40000000), %bb.10(0x40000000)
    liveins: $r0, $r1, $r2, $r3, $r12

    renamable $r6 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load (s8) from %ir.arrayidx.epil)
    t2CMPri renamable $r12, 1, 14, $noreg, implicit-def $cpsr
    renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load (s8) from %ir.arrayidx1.epil)
    renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14, $noreg
    tSTRBr killed renamable $r6, renamable $r0, $r3, 14, $noreg :: (store (s8) into %ir.arrayidx4.epil)
    tBcc %bb.11, 0, killed $cpsr

  bb.10.for.body.epil.1:
    successors: %bb.11(0x40000000), %bb.12(0x40000000)
    liveins: $r0, $r1, $r2, $r3, $r12

    renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14, $noreg
    t2CMPri killed renamable $r12, 2, 14, $noreg, implicit-def $cpsr
    renamable $r5 = tLDRBr renamable $r1, $r6, 14, $noreg :: (load (s8) from %ir.arrayidx.epil.1)
    renamable $r4 = tLDRBr renamable $r2, $r6, 14, $noreg :: (load (s8) from %ir.arrayidx1.epil.1)
    renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14, $noreg
    tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14, $noreg :: (store (s8) into %ir.arrayidx4.epil.1)
    tBcc %bb.12, 1, killed $cpsr

  bb.11.for.cond.cleanup:
    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11
    tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc

  bb.12.for.body.epil.2:
    liveins: $r0, $r1, $r2, $r3

    renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14, $noreg
    renamable $r1 = tLDRBr killed renamable $r1, $r3, 14, $noreg :: (load (s8) from %ir.arrayidx.epil.2)
    renamable $r2 = tLDRBr killed renamable $r2, $r3, 14, $noreg :: (load (s8) from %ir.arrayidx1.epil.2)
    renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg
    tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14, $noreg :: (store (s8) into %ir.arrayidx4.epil.2)
    $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11
    tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc

...