1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
--- |
define hidden void @vector_spill_in_loop() {
entry:
ret void
}
define hidden void @vector_spill_load_outside() {
entry:
ret void
}
...
---
name: vector_spill_in_loop
tracksRegLiveness: true
stack:
- { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body: |
; CHECK-LABEL: name: vector_spill_in_loop
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: $lr = MVE_DLSTP_16 renamable $r3
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r10, $r11, $r12
; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 0, $noreg, $noreg
; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 0, $noreg, $noreg
; CHECK: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 0, $noreg, $noreg, undef renamable $q5
; CHECK: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 0, killed $noreg, $noreg
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.1
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.3:
; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0:
successors: %bb.1(0x80000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
$r6 = tMOVr $r2, 14 /* CC::al */, $noreg
$r0 = tMOVr $r12, 14 /* CC::al */, $noreg
$r9 = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3
bb.1:
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr
renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
MVE_VPST 8, implicit $vpr
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg
bb.2:
successors: %bb.3(0x04000000), %bb.0(0x7c000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
bb.3:
$sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
$sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
...
---
name: vector_spill_load_outside
stack:
- { id: 0, name: '', type: spill-slot, offset: -120, size: 16, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
tracksRegLiveness: true
body: |
; CHECK-LABEL: name: vector_spill_load_outside
; CHECK: bb.0:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: $r6 = tMOVr $r2, 14 /* CC::al */, $noreg
; CHECK: $r0 = tMOVr $r12, 14 /* CC::al */, $noreg
; CHECK: $r9 = tMOVr $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS renamable $r1
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
; CHECK: liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
; CHECK: renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
; CHECK: renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
; CHECK: MVE_VPST 2, implicit $vpr
; CHECK: renamable $q5 = MVE_VSHR_immu16 killed renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
; CHECK: renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
; CHECK: MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
; CHECK: MVE_VPST 8, implicit $vpr
; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK: MVE_VPST 1, implicit $vpr
; CHECK: dead renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.1
; CHECK: bb.2:
; CHECK: successors: %bb.3(0x04000000), %bb.0(0x7c000000)
; CHECK: liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
; CHECK: dead renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
; CHECK: renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.3:
; CHECK: $sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
; CHECK: $sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
; CHECK: $sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
bb.0:
successors: %bb.1(0x80000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
$r6 = tMOVr $r2, 14 /* CC::al */, $noreg
$r0 = tMOVr $r12, 14 /* CC::al */, $noreg
$r9 = tMOVr $r3, 14 /* CC::al */, $noreg
renamable $lr = t2DoLoopStartTP renamable $r1, renamable $r3
bb.1:
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
liveins: $lr, $q0, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r11, $r12
renamable $vpr = MVE_VCTP16 renamable $r9, 0, $noreg, $noreg
MVE_VPST 8, implicit $vpr
renamable $r0, renamable $q6 = MVE_VLDRHU16_post killed renamable $r0, 16, 1, renamable $vpr, $noreg
renamable $q3 = MVE_VLDRHU16 renamable $r6, 0, 1, renamable $vpr, $noreg
MVE_VPST 2, implicit $vpr
renamable $q5 = MVE_VSHR_immu16 renamable $q3, 11, 1, renamable $vpr, $noreg, undef renamable $q5
renamable $r9 = nsw t2SUBri killed renamable $r9, 8, 14 /* CC::al */, $noreg, $noreg
MVE_VSTRWU32 killed renamable $q5, $sp, 80, 0, $noreg, $noreg :: (store (s128) into %stack.0, align 8)
MVE_VPST 8, implicit $vpr
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
MVE_VPST 1, implicit $vpr
renamable $vpr = MVE_VCMPi16r killed renamable $q6, renamable $r8, 1, 1, killed renamable $vpr, $noreg
renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
tB %bb.2, 14 /* CC::al */, $noreg
bb.2:
successors: %bb.3(0x04000000), %bb.0(0x7c000000)
liveins: $q0, $r1, $r2, $r3, $r4, $r5, $r7, $r8, $r10, $r11, $r12
renamable $q7 = MVE_VLDRWU32 $sp, 80, 0, $noreg, $noreg :: (load (s128) from %stack.0, align 8)
renamable $r0 = tLDRspi $sp, 1, 14 /* CC::al */, $noreg
renamable $r10 = nuw t2ADDri killed renamable $r10, 1, 14 /* CC::al */, $noreg, $noreg
renamable $r12 = t2ADDrs killed renamable $r12, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 3, 14 /* CC::al */, $noreg
renamable $r2 = t2ADDrs killed renamable $r2, killed renamable $r0, 10, 14 /* CC::al */, $noreg, $noreg
renamable $r0 = tLDRspi $sp, 2, 14 /* CC::al */, $noreg
tCMPhir renamable $r10, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
tBcc %bb.0, 1 /* CC::ne */, killed $cpsr
bb.3:
$sp = frame-destroy tADDspi $sp, 24, 14 /* CC::al */, $noreg
$sp = frame-destroy VLDMDIA_UPD $sp, 14 /* CC::al */, $noreg, def $d8, def $d9, def $d10, def $d11, def $d12, def $d13, def $d14, def $d15
$sp = frame-destroy tADDspi $sp, 1, 14 /* CC::al */, $noreg
$sp = frame-destroy t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc
...
|