1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
|
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX2
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl,+avx512bw -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512BWVL
--- |
define <32 x i8> @test_add_v32i8(<32 x i8> %arg1, <32 x i8> %arg2) {
%ret = add <32 x i8> %arg1, %arg2
ret <32 x i8> %ret
}
define <16 x i16> @test_add_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) {
%ret = add <16 x i16> %arg1, %arg2
ret <16 x i16> %ret
}
define <8 x i32> @test_add_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) {
%ret = add <8 x i32> %arg1, %arg2
ret <8 x i32> %ret
}
define <4 x i64> @test_add_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) {
%ret = add <4 x i64> %arg1, %arg2
ret <4 x i64> %ret
}
...
---
name: test_add_v32i8
# ALL-LABEL: name: test_add_v32i8
alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
# AVX2: %2:vr256 = VPADDBYrr %0, %1
#
# AVX512VL: %2:vr256 = VPADDBYrr %0, %1
#
# AVX512BWVL: %2:vr256x = VPADDBZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
%0(<32 x s8>) = COPY $ymm0
%1(<32 x s8>) = COPY $ymm1
%2(<32 x s8>) = G_ADD %0, %1
$ymm0 = COPY %2(<32 x s8>)
RET 0, implicit $ymm0
...
---
name: test_add_v16i16
# ALL-LABEL: name: test_add_v16i16
alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
# AVX2: %2:vr256 = VPADDWYrr %0, %1
#
# AVX512VL: %2:vr256 = VPADDWYrr %0, %1
#
# AVX512BWVL: %2:vr256x = VPADDWZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
%0(<16 x s16>) = COPY $ymm0
%1(<16 x s16>) = COPY $ymm1
%2(<16 x s16>) = G_ADD %0, %1
$ymm0 = COPY %2(<16 x s16>)
RET 0, implicit $ymm0
...
---
name: test_add_v8i32
# ALL-LABEL: name: test_add_v8i32
alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
# AVX2: %2:vr256 = VPADDDYrr %0, %1
#
# AVX512VL: %2:vr256x = VPADDDZ256rr %0, %1
#
# AVX512BWVL: %2:vr256x = VPADDDZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
%0(<8 x s32>) = COPY $ymm0
%1(<8 x s32>) = COPY $ymm1
%2(<8 x s32>) = G_ADD %0, %1
$ymm0 = COPY %2(<8 x s32>)
RET 0, implicit $ymm0
...
---
name: test_add_v4i64
# ALL-LABEL: name: test_add_v4i64
alignment: 16
legalized: true
regBankSelected: true
# AVX2: registers:
# AVX2-NEXT: - { id: 0, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 1, class: vr256, preferred-register: '' }
# AVX2-NEXT: - { id: 2, class: vr256, preferred-register: '' }
#
# AVX512VL: registers:
# AVX512VL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512VL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
#
# AVX512BWVL: registers:
# AVX512BWVL-NEXT: - { id: 0, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 1, class: vr256x, preferred-register: '' }
# AVX512BWVL-NEXT: - { id: 2, class: vr256x, preferred-register: '' }
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
- { id: 2, class: vecr }
# AVX2: %2:vr256 = VPADDQYrr %0, %1
#
# AVX512VL: %2:vr256x = VPADDQZ256rr %0, %1
#
# AVX512BWVL: %2:vr256x = VPADDQZ256rr %0, %1
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
%0(<4 x s64>) = COPY $ymm0
%1(<4 x s64>) = COPY $ymm1
%2(<4 x s64>) = G_ADD %0, %1
$ymm0 = COPY %2(<4 x s64>)
RET 0, implicit $ymm0
...
|
