1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefix=CHECK
define void @test_compress_undef_float_passthrough() {
; CHECK-LABEL: test_compress_undef_float_passthrough:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $5, %al
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: vcompresspd %ymm0, %ymm0 {%k1} {z}
; CHECK-NEXT: vscatterqpd %ymm0, (,%ymm0) {%k1}
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry: ; preds = %loop.50
%0 = bitcast i4 undef to <4 x i1>
%1 = call <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double> undef, <4 x double> undef, <4 x i1> <i1 1, i1 0, i1 1, i1 0>)
call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> %1, <4 x ptr> undef, i32 0, <4 x i1> %0)
ret void
}
; Function Attrs: nounwind readnone
declare <4 x double> @llvm.x86.avx512.mask.compress.v4f64(<4 x double>, <4 x double>, <4 x i1>)
; Function Attrs: nocallback nofree nosync nounwind willreturn writeonly
declare void @llvm.masked.scatter.v4f64.v4p0(<4 x double>, <4 x ptr>, i32 immarg, <4 x i1>)
|
