1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
|
// RUN: llvm-tblgen -gen-instr-info -I %p/../../include %s | FileCheck %s
// Check that getOperandType has the expected info in it
include "llvm/Target/Target.td"
def archInstrInfo : InstrInfo { }
def arch : Target {
let InstructionSet = archInstrInfo;
}
def Reg : Register<"reg">;
def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
def OpA : Operand<i32>;
def OpB : Operand<i32>;
def RegOp : RegisterOperand<RegClass>;
def InstA : Instruction {
let Size = 1;
let OutOperandList = (outs OpA:$a);
let InOperandList = (ins OpB:$b, i32imm:$c);
field bits<8> Inst;
field bits<8> SoftFail = 0;
let Namespace = "MyNamespace";
}
def InstB : Instruction {
let Size = 1;
let OutOperandList = (outs i32imm:$d);
let InOperandList = (ins unknown:$x);
field bits<8> Inst;
field bits<8> SoftFail = 0;
let Namespace = "MyNamespace";
}
def InstC : Instruction {
let Size = 1;
let OutOperandList = (outs RegClass:$d);
let InOperandList = (ins RegOp:$x);
field bits<8> Inst;
field bits<8> SoftFail = 0;
let Namespace = "MyNamespace";
}
// CHECK: #ifdef GET_INSTRINFO_OPERAND_TYPE
// CHECK: OpcodeOperandTypes[] = {
// CHECK: /* InstA */
// CHECK-NEXT: OpA, OpB, i32imm,
// CHECK-NEXT: /* InstB */
// CHECK-NEXT: i32imm, -1,
// CHECK-NEXT: /* InstC */
// CHECK-NEXT: RegClass, RegOp,
// CHECK: #endif // GET_INSTRINFO_OPERAND_TYPE
|
