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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -stop-after=finalize-isel -debug-only=isel -o /dev/null %s 2>&1 | FileCheck %s
define i64 @i64_test(i64 %i) nounwind readnone {
; CHECK-LABEL: i64_test:
; CHECK: SelectionDAG has 9 nodes:
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t11: ch,glue = CopyToReg t0, Register:i32 $vgpr0, IMPLICIT_DEF:i32
; CHECK-NEXT: t17: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
; CHECK-NEXT: t13: ch,glue = CopyToReg t11, Register:i32 $vgpr1, t17, t11:1
; CHECK-NEXT: t14: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t13, t13:1
; CHECK-EMPTY:
%loc = alloca i64
%j = load i64, i64 * %loc
%r = add i64 %i, %j
ret i64 %r
}
define i64 @i32_test(i32 %i) nounwind readnone {
; CHECK-LABEL: i32_test:
; CHECK: SelectionDAG has 8 nodes:
; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
; CHECK-EMPTY:
%loc = alloca i32
%j = load i32, i32 * %loc
%r = add i32 %i, %j
%ext = zext i32 %r to i64
ret i64 %ext
}
define i64 @i16_test(i16 %i) nounwind readnone {
; CHECK-LABEL: i16_test:
; CHECK: SelectionDAG has 8 nodes:
; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
; CHECK-EMPTY:
%loc = alloca i16
%j = load i16, i16 * %loc
%r = add i16 %i, %j
%ext = zext i16 %r to i64
ret i64 %ext
}
define i64 @i8_test(i8 %i) nounwind readnone {
; CHECK-LABEL: i8_test:
; CHECK: SelectionDAG has 8 nodes:
; CHECK-NEXT: t5: i32 = V_MOV_B32_e32 TargetConstant:i32<0>
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t7: ch,glue = CopyToReg t0, Register:i32 $vgpr0, t5
; CHECK-NEXT: t9: ch,glue = CopyToReg t7, Register:i32 $vgpr1, t5, t7:1
; CHECK-NEXT: t10: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t9, t9:1
; CHECK-EMPTY:
%loc = alloca i8
%j = load i8, i8 * %loc
%r = add i8 %i, %j
%ext = zext i8 %r to i64
ret i64 %ext
}
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