File: riscv32-zknd.c

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llvm-toolchain-17 1%3A17.0.6-22
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv32 -target-feature +zknd -emit-llvm %s -o - \
// RUN:     -disable-O0-optnone | opt -S -passes=mem2reg \
// RUN:     | FileCheck %s  -check-prefix=RV32ZKND

#include <stdint.h>

// RV32ZKND-LABEL: @aes32dsi(
// RV32ZKND-NEXT:  entry:
// RV32ZKND-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.aes32dsi(i32 [[RS1:%.*]], i32 [[RS2:%.*]], i32 3)
// RV32ZKND-NEXT:    ret i32 [[TMP0]]
//
uint32_t aes32dsi(uint32_t rs1, uint32_t rs2) {
  return __builtin_riscv_aes32dsi(rs1, rs2, 3);
}

// RV32ZKND-LABEL: @aes32dsmi(
// RV32ZKND-NEXT:  entry:
// RV32ZKND-NEXT:    [[TMP0:%.*]] = call i32 @llvm.riscv.aes32dsmi(i32 [[RS1:%.*]], i32 [[RS2:%.*]], i32 3)
// RV32ZKND-NEXT:    ret i32 [[TMP0]]
//
uint32_t aes32dsmi(uint32_t rs1, uint32_t rs2) {
  return __builtin_riscv_aes32dsmi(rs1, rs2, 3);
}