File: HexagonPatternsV65.td

package info (click to toggle)
llvm-toolchain-17 1%3A17.0.6-22
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 1,799,624 kB
  • sloc: cpp: 6,428,607; ansic: 1,383,196; asm: 793,408; python: 223,504; objc: 75,364; f90: 60,502; lisp: 33,869; pascal: 15,282; sh: 9,684; perl: 7,453; ml: 4,937; awk: 3,523; makefile: 2,889; javascript: 2,149; xml: 888; fortran: 619; cs: 573
file content (78 lines) | stat: -rw-r--r-- 3,528 bytes parent folder | download | duplicates (21)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
//==- HexagonPatternsV65.td -------------------------------*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

multiclass vgathermh<RegisterClass RC> {
  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
                           ".error \"should not emit\" ",
                           []>;
}

multiclass vgathermw<RegisterClass RC> {
  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
  mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
                           ".error \"should not emit\" ",
                           []>;
}

multiclass vgathermhw<RegisterClass RC> {
  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
   mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                IntRegs:$Rt, ModRegs:$Mu, RC:$Vv),
                           ".error \"should not emit\" ",
                           []>;
}

defm V6_vgathermh_pseudo  : vgathermh<HvxVR>;
defm V6_vgathermw_pseudo  : vgathermw<HvxVR>;
defm V6_vgathermhw_pseudo  : vgathermhw<HvxWR>;

multiclass vgathermhq<RegisterClass RC1, RegisterClass RC2> {
  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess in
  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
                                RC1:$Vv),
                           ".error \"should not emit\" ",
                           []>;
}

multiclass vgathermwq<RegisterClass RC1, RegisterClass RC2> {
  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
  mayStore = 1, addrMode = BaseImmOffset, accessSize = WordAccess in
  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                                RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
                                RC1:$Vv),
                           ".error \"should not emit\" ",
                           []>;
}

multiclass vgathermhwq<RegisterClass RC1, RegisterClass RC2> {
  let isCodeGenOnly = 1, isPseudo = 1, mayLoad = 1,
  mayStore = 1, addrMode = BaseImmOffset, accessSize = HalfWordAccess  in
  def NAME : CVI_GATHER_TMP_LD_Resource_NoOpcode<(outs ),
                           (ins IntRegs:$_dst_, s4_0Imm:$Ii,
                              RC2:$Vq, IntRegs:$Rt, ModRegs:$Mu,
                              RC1:$Vv),
                           ".error \"should not emit\" ",
                           []>;
}

defm V6_vgathermhq_pseudo  : vgathermhq<HvxVR, HvxQR>;
defm V6_vgathermwq_pseudo  : vgathermwq<HvxVR, HvxQR>;
defm V6_vgathermhwq_pseudo  : vgathermhwq<HvxWR, HvxQR>;