1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=instsimplify -S < %s | FileCheck %s
declare i8 @llvm.sadd.sat.i8(i8, i8)
declare i8 @llvm.ssub.sat.i8(i8, i8)
declare i8 @llvm.uadd.sat.i8(i8, i8)
declare i8 @llvm.usub.sat.i8(i8, i8)
define i1 @uadd_sat_overflow(i8 %x, i8 %y) {
; CHECK-LABEL: @uadd_sat_overflow(
; CHECK-NEXT: ret i1 false
;
%lhs = or i8 %x, 128
%rhs = or i8 %y, 128
%exp = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 254
ret i1 %r
}
define i1 @uadd_sat_overflow_fail(i8 %x, i8 %y) {
; CHECK-LABEL: @uadd_sat_overflow_fail(
; CHECK-NEXT: [[LHS:%.*]] = or i8 [[X:%.*]], -128
; CHECK-NEXT: [[RHS:%.*]] = or i8 [[Y:%.*]], 126
; CHECK-NEXT: [[EXP:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[LHS]], i8 [[RHS]])
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[EXP]], -2
; CHECK-NEXT: ret i1 [[R]]
;
%lhs = or i8 %x, 128
%rhs = or i8 %y, 126
%exp = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 254
ret i1 %r
}
define i1 @usub_sat_overflow(i8 %x, i8 %y) {
; CHECK-LABEL: @usub_sat_overflow(
; CHECK-NEXT: ret i1 false
;
%lhs = and i8 %x, 127
%rhs = or i8 %y, 128
%exp = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 1
ret i1 %r
}
define i1 @usub_sat_overflow_fail(i8 %x, i8 %y) {
; CHECK-LABEL: @usub_sat_overflow_fail(
; CHECK-NEXT: [[LHS:%.*]] = and i8 [[X:%.*]], 127
; CHECK-NEXT: [[RHS:%.*]] = or i8 [[Y:%.*]], 126
; CHECK-NEXT: [[EXP:%.*]] = call i8 @llvm.usub.sat.i8(i8 [[LHS]], i8 [[RHS]])
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[EXP]], 1
; CHECK-NEXT: ret i1 [[R]]
;
%lhs = and i8 %x, 127
%rhs = or i8 %y, 126
%exp = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 1
ret i1 %r
}
define i1 @sadd_sat_overflow_pos(i8 %x, i8 %y) {
; CHECK-LABEL: @sadd_sat_overflow_pos(
; CHECK-NEXT: ret i1 false
;
%xx = and i8 %x, 127
%yy = and i8 %y, 127
%lhs = or i8 %xx, 64
%rhs = or i8 %yy, 65
%exp = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 128
ret i1 %r
}
define i1 @sadd_sat_low_bits(i8 %x, i8 %y) {
; CHECK-LABEL: @sadd_sat_low_bits(
; CHECK-NEXT: ret i1 false
;
%xx = and i8 %x, 15
%yy = and i8 %y, 15
%lhs = or i8 %xx, 1
%rhs = and i8 %yy, -2
%exp = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
%and = and i8 %exp, 1
%r = icmp eq i8 %and, 0
ret i1 %r
}
define i1 @sadd_sat_fail_may_overflow(i8 %x, i8 %y) {
; CHECK-LABEL: @sadd_sat_fail_may_overflow(
; CHECK-NEXT: [[LHS:%.*]] = or i8 [[X:%.*]], 1
; CHECK-NEXT: [[RHS:%.*]] = and i8 [[Y:%.*]], -2
; CHECK-NEXT: [[EXP:%.*]] = call i8 @llvm.sadd.sat.i8(i8 [[LHS]], i8 [[RHS]])
; CHECK-NEXT: [[AND:%.*]] = and i8 [[EXP]], 1
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%lhs = or i8 %x, 1
%rhs = and i8 %y, -2
%exp = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
%and = and i8 %exp, 1
%r = icmp eq i8 %and, 0
ret i1 %r
}
define i1 @sadd_sat_overflow_neg(i8 %x, i8 %y) {
; CHECK-LABEL: @sadd_sat_overflow_neg(
; CHECK-NEXT: ret i1 false
;
%lhs = or i8 %x, 192
%rhs = or i8 %y, 191
%exp = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 127
ret i1 %r
}
define i1 @ssub_sat_overflow_neg(i8 %x, i8 %y) {
; CHECK-LABEL: @ssub_sat_overflow_neg(
; CHECK-NEXT: ret i1 false
;
%xx = and i8 %x, 112
%yy = and i8 %y, 127
%lhs = or i8 %xx, 128
%rhs = or i8 %yy, 126
%exp = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 32
ret i1 %r
}
define i1 @ssub_sat_low_bits(i8 %x, i8 %y) {
; CHECK-LABEL: @ssub_sat_low_bits(
; CHECK-NEXT: ret i1 false
;
%xx = and i8 %x, 15
%yy = and i8 %y, 15
%lhs = or i8 %xx, 17
%rhs = and i8 %yy, -2
%exp = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
%and = and i8 %exp, 1
%r = icmp eq i8 %and, 0
ret i1 %r
}
define i1 @ssub_sat_fail_may_overflow(i8 %x, i8 %y) {
; CHECK-LABEL: @ssub_sat_fail_may_overflow(
; CHECK-NEXT: [[XX:%.*]] = and i8 [[X:%.*]], 15
; CHECK-NEXT: [[YY:%.*]] = and i8 [[Y:%.*]], 15
; CHECK-NEXT: [[LHS:%.*]] = or i8 [[XX]], 1
; CHECK-NEXT: [[RHS:%.*]] = and i8 [[YY]], -2
; CHECK-NEXT: [[EXP:%.*]] = call i8 @llvm.ssub.sat.i8(i8 [[LHS]], i8 [[RHS]])
; CHECK-NEXT: [[AND:%.*]] = and i8 [[EXP]], 1
; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[AND]], 0
; CHECK-NEXT: ret i1 [[R]]
;
%xx = and i8 %x, 15
%yy = and i8 %y, 15
%lhs = or i8 %xx, 1
%rhs = and i8 %yy, -2
%exp = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
%and = and i8 %exp, 1
%r = icmp eq i8 %and, 0
ret i1 %r
}
define i1 @ssub_sat_overflow_pos(i8 %x, i8 %y) {
; CHECK-LABEL: @ssub_sat_overflow_pos(
; CHECK-NEXT: ret i1 false
;
%xx = and i8 %x, 24
%yy = and i8 %y, 3
%lhs = or i8 %xx, 8
%rhs = or i8 %yy, 128
%exp = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
%r = icmp eq i8 %exp, 128
ret i1 %r
}
|