1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
target triple = "aarch64-unknown-linux-gnu"
define <8 x i16> @load_zext_v8i8i16(ptr %ap) {
; CHECK-LABEL: load_zext_v8i8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl8
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
%a = load <8 x i8>, ptr %ap
%val = zext <8 x i8> %a to <8 x i16>
ret <8 x i16> %val
}
define <4 x i32> @load_zext_v4i16i32(ptr %ap) {
; CHECK-LABEL: load_zext_v4i16i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
%a = load <4 x i16>, ptr %ap
%val = zext <4 x i16> %a to <4 x i32>
ret <4 x i32> %val
}
define <2 x i64> @load_zext_v2i32i64(ptr %ap) {
; CHECK-LABEL: load_zext_v2i32i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %ap
%val = zext <2 x i32> %a to <2 x i64>
ret <2 x i64> %val
}
define <2 x i256> @load_zext_v2i64i256(ptr %ap) {
; CHECK-LABEL: load_zext_v2i64i256:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: mov x2, xzr
; CHECK-NEXT: mov x3, xzr
; CHECK-NEXT: mov x5, xzr
; CHECK-NEXT: mov x6, xzr
; CHECK-NEXT: mov z1.d, z0.d[1]
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: fmov x4, d1
; CHECK-NEXT: mov x7, xzr
; CHECK-NEXT: ret
%a = load <2 x i64>, ptr %ap
%val = zext <2 x i64> %a to <2 x i256>
ret <2 x i256> %val
}
define <16 x i32> @load_sext_v16i8i32(ptr %ap) {
; CHECK-LABEL: load_sext_v16i8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #4 // =0x4
; CHECK-NEXT: mov w9, #8 // =0x8
; CHECK-NEXT: mov w10, #12 // =0xc
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ld1sb { z1.s }, p0/z, [x0, x8]
; CHECK-NEXT: ld1sb { z2.s }, p0/z, [x0, x9]
; CHECK-NEXT: ld1sb { z3.s }, p0/z, [x0, x10]
; CHECK-NEXT: ld1sb { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: ret
%a = load <16 x i8>, ptr %ap
%val = sext <16 x i8> %a to <16 x i32>
ret <16 x i32> %val
}
define <8 x i32> @load_sext_v8i16i32(ptr %ap) {
; CHECK-LABEL: load_sext_v8i16i32:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ld1sh { z1.s }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: ret
%a = load <8 x i16>, ptr %ap
%val = sext <8 x i16> %a to <8 x i32>
ret <8 x i32> %val
}
define <4 x i256> @load_sext_v4i32i256(ptr %ap) {
; CHECK-LABEL: load_sext_v4i32i256:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: sunpklo z1.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: fmov x9, d1
; CHECK-NEXT: sunpklo z0.d, z0.s
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: mov z0.d, z0.d[1]
; CHECK-NEXT: asr x10, x9, #63
; CHECK-NEXT: asr x12, x11, #63
; CHECK-NEXT: stp x9, x10, [x8]
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: mov z0.d, z1.d[1]
; CHECK-NEXT: stp x11, x12, [x8, #64]
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: stp x10, x10, [x8, #16]
; CHECK-NEXT: stp x12, x12, [x8, #80]
; CHECK-NEXT: asr x10, x9, #63
; CHECK-NEXT: asr x12, x11, #63
; CHECK-NEXT: stp x10, x10, [x8, #112]
; CHECK-NEXT: stp x9, x10, [x8, #96]
; CHECK-NEXT: stp x12, x12, [x8, #48]
; CHECK-NEXT: stp x11, x12, [x8, #32]
; CHECK-NEXT: ret
%a = load <4 x i32>, ptr %ap
%val = sext <4 x i32> %a to <4 x i256>
ret <4 x i256> %val
}
define <2 x i256> @load_sext_v2i64i256(ptr %ap) {
; CHECK-LABEL: load_sext_v2i64i256:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: mov z0.d, z0.d[1]
; CHECK-NEXT: fmov x10, d0
; CHECK-NEXT: asr x9, x8, #63
; CHECK-NEXT: asr x11, x10, #63
; CHECK-NEXT: stp x8, x9, [sp, #-32]!
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: mov z0.d, x9
; CHECK-NEXT: stp x10, x11, [sp, #16]
; CHECK-NEXT: mov z1.d, z0.d[1]
; CHECK-NEXT: fmov x2, d0
; CHECK-NEXT: mov z0.d, x11
; CHECK-NEXT: fmov x3, d1
; CHECK-NEXT: ldp q1, q3, [sp], #32
; CHECK-NEXT: mov z2.d, z0.d[1]
; CHECK-NEXT: fmov x6, d0
; CHECK-NEXT: mov z0.d, z1.d[1]
; CHECK-NEXT: fmov x0, d1
; CHECK-NEXT: mov z1.d, z3.d[1]
; CHECK-NEXT: fmov x7, d2
; CHECK-NEXT: fmov x4, d3
; CHECK-NEXT: fmov x1, d0
; CHECK-NEXT: fmov x5, d1
; CHECK-NEXT: ret
%a = load <2 x i64>, ptr %ap
%val = sext <2 x i64> %a to <2 x i256>
ret <2 x i256> %val
}
define <16 x i64> @load_zext_v16i16i64(ptr %ap) {
; CHECK-LABEL: load_zext_v16i16i64:
; CHECK: // %bb.0:
; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: mov x9, #4 // =0x4
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: mov x10, #6 // =0x6
; CHECK-NEXT: mov x11, #8 // =0x8
; CHECK-NEXT: mov x12, #10 // =0xa
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: mov x8, #12 // =0xc
; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT: mov x9, #14 // =0xe
; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, x10, lsl #1]
; CHECK-NEXT: ld1h { z4.d }, p0/z, [x0, x11, lsl #1]
; CHECK-NEXT: ld1h { z5.d }, p0/z, [x0, x12, lsl #1]
; CHECK-NEXT: ld1h { z6.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1h { z7.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
; CHECK-NEXT: // kill: def $q2 killed $q2 killed $z2
; CHECK-NEXT: // kill: def $q3 killed $q3 killed $z3
; CHECK-NEXT: // kill: def $q4 killed $q4 killed $z4
; CHECK-NEXT: // kill: def $q5 killed $q5 killed $z5
; CHECK-NEXT: // kill: def $q6 killed $q6 killed $z6
; CHECK-NEXT: // kill: def $q7 killed $q7 killed $z7
; CHECK-NEXT: ret
%a = load <16 x i16>, ptr %ap
%val = zext <16 x i16> %a to <16 x i64>
ret <16 x i64> %val
}
|
