1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx90a -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s
---
name: assert_zext_vgpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: assert_zext_vgpr
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: %assert_zext:vgpr(s32) = G_ASSERT_ZEXT %copy, 4
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
%copy:_(s32) = COPY $vgpr0
%assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
S_ENDPGM 0, implicit %assert_zext
...
---
name: assert_zext_sgpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr8
; CHECK-LABEL: name: assert_zext_sgpr
; CHECK: liveins: $sgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:sgpr(s32) = COPY $sgpr8
; CHECK-NEXT: %assert_zext:sgpr(s32) = G_ASSERT_ZEXT %copy, 4
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
%copy:_(s32) = COPY $sgpr8
%assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
S_ENDPGM 0, implicit %assert_zext
...
---
name: assert_zext_agpr
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $agpr0
; CHECK-LABEL: name: assert_zext_agpr
; CHECK: liveins: $agpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:agpr(s32) = COPY $agpr0
; CHECK-NEXT: %assert_zext:agpr(s32) = G_ASSERT_ZEXT %copy, 4
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
%copy:_(s32) = COPY $agpr0
%assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
S_ENDPGM 0, implicit %assert_zext
...
---
name: assert_zext_vgpr_regclass
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: assert_zext_vgpr_regclass
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:vgpr_32(s32) = COPY $vgpr0
; CHECK-NEXT: %assert_zext:vgpr(s32) = G_ASSERT_ZEXT %copy, 4
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
%copy:vgpr_32(s32) = COPY $vgpr0
%assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
S_ENDPGM 0, implicit %assert_zext
...
---
name: assert_zext_sgpr_regcllass
alignment: 4
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr8
; CHECK-LABEL: name: assert_zext_sgpr_regcllass
; CHECK: liveins: $sgpr8
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %copy:sgpr_32(s32) = COPY $sgpr8
; CHECK-NEXT: %assert_zext:sgpr(s32) = G_ASSERT_ZEXT %copy, 4
; CHECK-NEXT: S_ENDPGM 0, implicit %assert_zext(s32)
%copy:sgpr_32(s32) = COPY $sgpr8
%assert_zext:_(s32) = G_ASSERT_ZEXT %copy, 4
S_ENDPGM 0, implicit %assert_zext
...
|
