1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,SDAG %s
; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GISEL %s
define float @v_exp2_f32(float %src) {
; GCN-LABEL: v_exp2_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f32_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
%exp2 = call float @llvm.amdgcn.exp2.f32(float %src)
ret float %exp2
}
define float @v_fabs_exp2_f32(float %src) {
; GCN-LABEL: v_fabs_exp2_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f32_e64 v0, |v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call float @llvm.fabs.f32(float %src)
%exp2 = call float @llvm.amdgcn.exp2.f32(float %fabs.src)
ret float %exp2
}
define float @v_fneg_fabs_exp2_f32(float %src) {
; GCN-LABEL: v_fneg_fabs_exp2_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f32_e64 v0, -|v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call float @llvm.fabs.f32(float %src)
%neg.fabs.src = fneg float %fabs.src
%exp2 = call float @llvm.amdgcn.exp2.f32(float %neg.fabs.src)
ret float %exp2
}
define half @v_exp2_f16(half %src) {
; GCN-LABEL: v_exp2_f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f16_e32 v0, v0
; GCN-NEXT: s_setpc_b64 s[30:31]
%exp2 = call half @llvm.amdgcn.exp2.f16(half %src)
ret half %exp2
}
define half @v_fabs_exp2_f16(half %src) {
; GCN-LABEL: v_fabs_exp2_f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f16_e64 v0, |v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call half @llvm.fabs.f16(half %src)
%exp2 = call half @llvm.amdgcn.exp2.f16(half %fabs.src)
ret half %exp2
}
define half @v_fneg_fabs_exp2_f16(half %src) {
; GCN-LABEL: v_fneg_fabs_exp2_f16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_exp_f16_e64 v0, -|v0|
; GCN-NEXT: s_setpc_b64 s[30:31]
%fabs.src = call half @llvm.fabs.f16(half %src)
%neg.fabs.src = fneg half %fabs.src
%exp2 = call half @llvm.amdgcn.exp2.f16(half %neg.fabs.src)
ret half %exp2
}
declare half @llvm.amdgcn.exp2.f16(half) #0
declare float @llvm.amdgcn.exp2.f32(float) #0
declare float @llvm.fabs.f32(float) #0
declare half @llvm.fabs.f16(half) #0
attributes #0 = { nounwind readnone speculatable willreturn }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GISEL: {{.*}}
; SDAG: {{.*}}
|
