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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs -stop-after=rewrite-partial-reg-uses %s -o - | FileCheck -check-prefix=CHECK %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -amdgpu-enable-rewrite-partial-reg-uses=true -verify-machineinstrs -start-before=rename-independent-subregs %s -o /dev/null 2>&1
---
name: test_subregs_composition_vreg_1024
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_composition_vreg_1024
; CHECK: undef %5.sub0:vreg_96 = V_MOV_B32_e32 1, implicit $exec
; CHECK-NEXT: %5.sub1:vreg_96 = V_MOV_B32_e32 2, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit %5.sub0_sub1
; CHECK-NEXT: S_NOP 0, implicit %5.sub1_sub2
; CHECK-NEXT: undef %6.sub0:vreg_128 = V_MOV_B32_e32 11, implicit $exec
; CHECK-NEXT: %6.sub1:vreg_128 = V_MOV_B32_e32 12, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit %6.sub0_sub1_sub2
; CHECK-NEXT: S_NOP 0, implicit %6.sub1_sub2_sub3
; CHECK-NEXT: undef %7.sub0:vreg_160 = V_MOV_B32_e32 21, implicit $exec
; CHECK-NEXT: %7.sub1:vreg_160 = V_MOV_B32_e32 22, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit %7.sub0_sub1_sub2_sub3
; CHECK-NEXT: S_NOP 0, implicit %7.sub1_sub2_sub3_sub4
; CHECK-NEXT: undef %8.sub0:vreg_192 = V_MOV_B32_e32 31, implicit $exec
; CHECK-NEXT: %8.sub1:vreg_192 = V_MOV_B32_e32 32, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit %8.sub0_sub1_sub2_sub3_sub4
; CHECK-NEXT: S_NOP 0, implicit %8.sub1_sub2_sub3_sub4_sub5
; CHECK-NEXT: undef %9.sub0:vreg_256 = V_MOV_B32_e32 41, implicit $exec
; CHECK-NEXT: %9.sub2:vreg_256 = V_MOV_B32_e32 43, implicit $exec
; CHECK-NEXT: S_NOP 0, implicit %9.sub0_sub1_sub2_sub3_sub4_sub5
; CHECK-NEXT: S_NOP 0, implicit %9.sub2_sub3_sub4_sub5_sub6_sub7
undef %0.sub1:vreg_1024 = V_MOV_B32_e32 01, implicit $exec
%0.sub2:vreg_1024 = V_MOV_B32_e32 02, implicit $exec
S_NOP 0, implicit %0.sub1_sub2
S_NOP 0, implicit %0.sub2_sub3
undef %1.sub1:vreg_1024 = V_MOV_B32_e32 11, implicit $exec
%1.sub2:vreg_1024 = V_MOV_B32_e32 12, implicit $exec
S_NOP 0, implicit %1.sub1_sub2_sub3
S_NOP 0, implicit %1.sub2_sub3_sub4
undef %2.sub1:vreg_1024 = V_MOV_B32_e32 21, implicit $exec
%2.sub2:vreg_1024 = V_MOV_B32_e32 22, implicit $exec
S_NOP 0, implicit %2.sub1_sub2_sub3_sub4
S_NOP 0, implicit %2.sub2_sub3_sub4_sub5
undef %3.sub1:vreg_1024 = V_MOV_B32_e32 31, implicit $exec
%3.sub2:vreg_1024 = V_MOV_B32_e32 32, implicit $exec
S_NOP 0, implicit %3.sub1_sub2_sub3_sub4_sub5
S_NOP 0, implicit %3.sub2_sub3_sub4_sub5_sub6
undef %4.sub1:vreg_1024 = V_MOV_B32_e32 41, implicit $exec
%4.sub3:vreg_1024 = V_MOV_B32_e32 43, implicit $exec
S_NOP 0, implicit %4.sub1_sub2_sub3_sub4_sub5_sub6
S_NOP 0, implicit %4.sub3_sub4_sub5_sub6_sub7_sub8
...
---
name: test_subregs_unknown_regclass_from_instructions
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions
; CHECK: undef %2.sub0:sgpr_64 = S_MOV_B32 1
; CHECK-NEXT: %2.sub1:sgpr_64 = S_MOV_B32 2
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY %2
undef %0.sub4:sgpr_1024 = S_MOV_B32 01
%0.sub5:sgpr_1024 = S_MOV_B32 02
%1:vreg_64 = COPY %0.sub4_sub5
...
---
name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
tracksRegLiveness: true
registers:
- { id: 0, class: sgpr_1024 }
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_unknown_regclass_from_instructions_sgpr_1024_to_sgpr_64
; CHECK: dead [[COPY:%[0-9]+]]:vreg_64 = COPY undef %2:sgpr_64
%1:vreg_64 = COPY undef %0.sub4_sub5
...
---
name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_subregs_regclass_defined_by_dst_operand_sreg_64_xexec
; CHECK: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]
undef %0.sub2_sub3:sgpr_128 = S_LOAD_DWORDX2_IMM undef %1:sreg_64, 0, 0
%2:vreg_64 = COPY %0.sub2_sub3:sgpr_128
...
|
