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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s
define amdgpu_kernel void @sdwa_test() local_unnamed_addr #0 {
; GFX9-LABEL: sdwa_test:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: v_add_u32_e32 v1, 10, v0
; GFX9-NEXT: v_add_u32_e32 v0, 20, v0
; GFX9-NEXT: v_add_co_u32_sdwa v0, vcc, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[0:1], 0, 0, vcc
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[0:1], off
; GFX9-NEXT: s_endpgm
bb:
%tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%v0 = add i32 %tid, 10
%v1 = add i32 %tid, 20
%v2 = zext i32 %v0 to i64
%v3 = zext i32 %v1 to i64
%v.t = and i64 %v3, 255
%v4 = add i64 %v2, %v.t
store i64 %v4, ptr addrspace(1) undef
ret void
}
define amdgpu_kernel void @test_add_co_sdwa(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) #0 {
; GFX9-LABEL: test_add_co_sdwa:
; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v4, v2, s[2:3]
; GFX9-NEXT: global_load_dwordx2 v[0:1], v3, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_co_u32_sdwa v0, vcc, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: global_store_dwordx2 v3, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tmp
%tmp4 = load i32, ptr addrspace(1) %tmp3, align 4
%tmp5 = and i32 %tmp4, 255
%tmp6 = zext i32 %tmp5 to i64
%tmp7 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tmp
%tmp8 = load i64, ptr addrspace(1) %tmp7, align 8
%tmp9 = add nsw i64 %tmp8, %tmp6
store i64 %tmp9, ptr addrspace(1) %tmp7, align 8
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()
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