File: and-add-lsr.ll

package info (click to toggle)
llvm-toolchain-17 1%3A17.0.6-22
  • links: PTS, VCS
  • area: main
  • in suites: forky, sid, trixie
  • size: 1,799,624 kB
  • sloc: cpp: 6,428,607; ansic: 1,383,196; asm: 793,408; python: 223,504; objc: 75,364; f90: 60,502; lisp: 33,869; pascal: 15,282; sh: 9,684; perl: 7,453; ml: 4,937; awk: 3,523; makefile: 2,889; javascript: 2,149; xml: 888; fortran: 619; cs: 573
file content (25 lines) | stat: -rw-r--r-- 753 bytes parent folder | download | duplicates (3) 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
 
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV64I

define i32 @and_add_lsr(i32 %x, i32 %y) {
; RV32I-LABEL: and_add_lsr:
; RV32I:       # %bb.0:
; RV32I-NEXT:    addi a0, a0, -1
; RV32I-NEXT:    srli a1, a1, 20
; RV32I-NEXT:    and a0, a1, a0
; RV32I-NEXT:    ret
;
; RV64I-LABEL: and_add_lsr:
; RV64I:       # %bb.0:
; RV64I-NEXT:    addiw a0, a0, -1
; RV64I-NEXT:    srliw a1, a1, 20
; RV64I-NEXT:    and a0, a1, a0
; RV64I-NEXT:    ret
  %1 = add i32 %x, 4095
  %2 = lshr i32 %y, 20
  %r = and i32 %2, %1
  ret i32 %r
}