1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+zbc -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBC-ZBKC
; RUN: llc -mtriple=riscv64 -mattr=+zbkc -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64ZBC-ZBKC
declare i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
define i64 @clmul64(i64 %a, i64 %b) nounwind {
; RV64ZBC-ZBKC-LABEL: clmul64:
; RV64ZBC-ZBKC: # %bb.0:
; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a1
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmul.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
define i64 @clmul64h(i64 %a, i64 %b) nounwind {
; RV64ZBC-ZBKC-LABEL: clmul64h:
; RV64ZBC-ZBKC: # %bb.0:
; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a1
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i64 @llvm.riscv.clmulh.i64(i64 %a, i64 %b)
ret i64 %tmp
}
declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
define signext i32 @clmul32(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBC-ZBKC-LABEL: clmul32:
; RV64ZBC-ZBKC: # %bb.0:
; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a1
; RV64ZBC-ZBKC-NEXT: sext.w a0, a0
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
ret i32 %tmp
}
declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
define signext i32 @clmul32h(i32 signext %a, i32 signext %b) nounwind {
; RV64ZBC-ZBKC-LABEL: clmul32h:
; RV64ZBC-ZBKC: # %bb.0:
; RV64ZBC-ZBKC-NEXT: slli a1, a1, 32
; RV64ZBC-ZBKC-NEXT: slli a0, a0, 32
; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a1
; RV64ZBC-ZBKC-NEXT: srai a0, a0, 32
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
ret i32 %tmp
}
; FIXME: We could avoid the slli instructions by using clmul+srai since the
; inputs are zero extended.
define signext i32 @clmul32h_zext(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV64ZBC-ZBKC-LABEL: clmul32h_zext:
; RV64ZBC-ZBKC: # %bb.0:
; RV64ZBC-ZBKC-NEXT: slli a1, a1, 32
; RV64ZBC-ZBKC-NEXT: slli a0, a0, 32
; RV64ZBC-ZBKC-NEXT: clmulh a0, a0, a1
; RV64ZBC-ZBKC-NEXT: srai a0, a0, 32
; RV64ZBC-ZBKC-NEXT: ret
%tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
ret i32 %tmp
}
|
