1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x double> @vfwmul_vv_nxv1f64(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwmul.vv v10, v8, v9
; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
%ve = fmul <vscale x 1 x double> %vc, %vd
ret <vscale x 1 x double> %ve
}
define <vscale x 1 x double> @vfwmul_vf_nxv1f64(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwmul.vf v9, v8, fa0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
%ve = fmul <vscale x 1 x double> %vc, %vd
ret <vscale x 1 x double> %ve
}
define <vscale x 1 x double> @vfwmul_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv1f64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vfwmul.vf v9, v8, fa0
; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret
%fpext = fpext float %b to double
%head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
%splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
%vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
%ve = fmul <vscale x 1 x double> %vc, %splat
ret <vscale x 1 x double> %ve
}
define <vscale x 2 x double> @vfwmul_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwmul.vv v10, v8, v9
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
%ve = fmul <vscale x 2 x double> %vc, %vd
ret <vscale x 2 x double> %ve
}
define <vscale x 2 x double> @vfwmul_vf_nxv2f64(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwmul.vf v10, v8, fa0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
%ve = fmul <vscale x 2 x double> %vc, %vd
ret <vscale x 2 x double> %ve
}
define <vscale x 2 x double> @vfwmul_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv2f64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vfwmul.vf v10, v8, fa0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
%fpext = fpext float %b to double
%head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
%splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
%vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
%ve = fmul <vscale x 2 x double> %vc, %splat
ret <vscale x 2 x double> %ve
}
define <vscale x 4 x double> @vfwmul_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwmul.vv v12, v8, v10
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
%ve = fmul <vscale x 4 x double> %vc, %vd
ret <vscale x 4 x double> %ve
}
define <vscale x 4 x double> @vfwmul_vf_nxv4f64(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwmul.vf v12, v8, fa0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
%ve = fmul <vscale x 4 x double> %vc, %vd
ret <vscale x 4 x double> %ve
}
define <vscale x 4 x double> @vfwmul_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv4f64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfwmul.vf v12, v8, fa0
; CHECK-NEXT: vmv4r.v v8, v12
; CHECK-NEXT: ret
%fpext = fpext float %b to double
%head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
%splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
%vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
%ve = fmul <vscale x 4 x double> %vc, %splat
ret <vscale x 4 x double> %ve
}
define <vscale x 8 x double> @vfwmul_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwmul.vv v16, v8, v12
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
%ve = fmul <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
define <vscale x 8 x double> @vfwmul_vf_nxv8f64(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwmul.vf v16, v8, fa0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x float> poison, float %b, i32 0
%splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
%ve = fmul <vscale x 8 x double> %vc, %vd
ret <vscale x 8 x double> %ve
}
define <vscale x 8 x double> @vfwmul_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv8f64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfwmul.vf v16, v8, fa0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: ret
%fpext = fpext float %b to double
%head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
%splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
%vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
%ve = fmul <vscale x 8 x double> %vc, %splat
ret <vscale x 8 x double> %ve
}
|
