1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64I
define void @sext_shl_trunc_same_size(i16 %x, i32 %y, ptr %res) {
; RV32I-LABEL: sext_shl_trunc_same_size:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: sh a0, 0(a2)
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_shl_trunc_same_size:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: sh a0, 0(a2)
; RV64I-NEXT: ret
%conv = sext i16 %x to i32
%shl = shl i32 %conv, %y
%t = trunc i32 %shl to i16
store i16 %t, ptr %res
ret void
}
define void @zext_shl_trunc_same_size(i16 %x, i32 %y, ptr %res) {
; RV32I-LABEL: zext_shl_trunc_same_size:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: sh a0, 0(a2)
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_shl_trunc_same_size:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: sh a0, 0(a2)
; RV64I-NEXT: ret
%conv = zext i16 %x to i32
%shl = shl i32 %conv, %y
%t = trunc i32 %shl to i16
store i16 %t, ptr %res
ret void
}
define void @sext_shl_trunc_smaller(i16 %x, i32 %y, ptr %res) {
; RV32I-LABEL: sext_shl_trunc_smaller:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_shl_trunc_smaller:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: sb a0, 0(a2)
; RV64I-NEXT: ret
%conv = sext i16 %x to i32
%shl = shl i32 %conv, %y
%t = trunc i32 %shl to i8
store i8 %t, ptr %res
ret void
}
define void @zext_shl_trunc_smaller(i16 %x, i32 %y, ptr %res) {
; RV32I-LABEL: zext_shl_trunc_smaller:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: sb a0, 0(a2)
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_shl_trunc_smaller:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: sb a0, 0(a2)
; RV64I-NEXT: ret
%conv = zext i16 %x to i32
%shl = shl i32 %conv, %y
%t = trunc i32 %shl to i8
store i8 %t, ptr %res
ret void
}
; negative test - demanding 1 high-bit too many to change the extend
define signext i17 @sext_shl_trunc_larger(i16 %x, i32 %y) {
; RV32I-LABEL: sext_shl_trunc_larger:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: slli a0, a0, 15
; RV32I-NEXT: srai a0, a0, 15
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_shl_trunc_larger:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 47
; RV64I-NEXT: srai a0, a0, 47
; RV64I-NEXT: ret
%conv = sext i16 %x to i32
%shl = shl i32 %conv, %y
%t = trunc i32 %shl to i17
ret i17 %t
}
; negative test - demanding 1 high-bit too many to change the extend
define zeroext i17 @zext_shl_trunc_larger(i16 %x, i32 %y) {
; RV32I-LABEL: zext_shl_trunc_larger:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: slli a0, a0, 15
; RV32I-NEXT: srli a0, a0, 15
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_shl_trunc_larger:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 47
; RV64I-NEXT: srli a0, a0, 47
; RV64I-NEXT: ret
%conv = zext i16 %x to i32
%shl = shl i32 %conv, %y
%t = trunc i32 %shl to i17
ret i17 %t
}
define i32 @sext_shl_mask(i16 %x, i32 %y) {
; RV32I-LABEL: sext_shl_mask:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_shl_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
%conv = sext i16 %x to i32
%shl = shl i32 %conv, %y
%t = and i32 %shl, 65535
ret i32 %t
}
define i32 @zext_shl_mask(i16 %x, i32 %y) {
; RV32I-LABEL: zext_shl_mask:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_shl_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: ret
%conv = zext i16 %x to i32
%shl = shl i32 %conv, %y
%t = and i32 %shl, 65535
ret i32 %t
}
; negative test - demanding a bit that could change with sext
define i32 @sext_shl_mask_higher(i16 %x, i32 %y) {
; RV32I-LABEL: sext_shl_mask_higher:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sext_shl_mask_higher:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
%conv = sext i16 %x to i32
%shl = shl i32 %conv, %y
%t = and i32 %shl, 65536
ret i32 %t
}
; negative test - demanding a bit that could change with zext
define i32 @zext_shl_mask_higher(i16 %x, i32 %y) {
; RV32I-LABEL: zext_shl_mask_higher:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srli a0, a0, 16
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: zext_shl_mask_higher:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srli a0, a0, 48
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: ret
%conv = zext i16 %x to i32
%shl = shl i32 %conv, %y
%t = and i32 %shl, 65536
ret i32 %t
}
; May need some, but not all of the bits set by the 'or'.
define i32 @set_shl_mask(i32 %x, i32 %y) {
; RV32I-LABEL: set_shl_mask:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, 1
; RV32I-NEXT: or a0, a0, a3
; RV32I-NEXT: sll a0, a0, a1
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: set_shl_mask:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 16
; RV64I-NEXT: addiw a3, a2, 1
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: sllw a0, a0, a1
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: ret
%z = or i32 %x, 196609
%s = shl i32 %z, %y
%r = and i32 %s, 65536
ret i32 %r
}
|
