1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+zbb -O3 < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64I
; RUN: llc -mtriple=riscv64 -mattr=+zbb,+f -target-abi=lp64f -O3 < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-RV64IF
; Tests aimed to check optimization which combines
; two comparison operations and logic operation into
; one select(min/max) operation and one comparison
; operaion.
; 4 patterns below will be converted to umin+less.
define i1 @ulo(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ulo:
; CHECK: # %bb.0:
; CHECK-NEXT: minu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ult i64 %a, %c
%l1 = icmp ult i64 %b, %c
%res = or i1 %l0, %l1
ret i1 %res
}
define i1 @ulo_swap1(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ulo_swap1:
; CHECK: # %bb.0:
; CHECK-NEXT: minu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %c, %a
%l1 = icmp ult i64 %b, %c
%res = or i1 %l0, %l1
ret i1 %res
}
define i1 @ulo_swap2(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ulo_swap2:
; CHECK: # %bb.0:
; CHECK-NEXT: minu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ult i64 %a, %c
%l1 = icmp ugt i64 %c, %b
%res = or i1 %l0, %l1
ret i1 %res
}
define i1 @ulo_swap12(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ulo_swap12:
; CHECK: # %bb.0:
; CHECK-NEXT: minu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %c, %a
%l1 = icmp ugt i64 %c, %b
%res = or i1 %l0, %l1
ret i1 %res
}
; 4 patterns below will be converted to umax+less.
define i1 @ula(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ula:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ult i64 %a, %c
%l1 = icmp ult i64 %b, %c
%res = and i1 %l0, %l1
ret i1 %res
}
define i1 @ula_swap1(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ula_swap1:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %c, %a
%l1 = icmp ult i64 %b, %c
%res = and i1 %l0, %l1
ret i1 %res
}
define i1 @ula_swap2(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ula_swap2:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ult i64 %a, %c
%l1 = icmp ugt i64 %c, %b
%res = and i1 %l0, %l1
ret i1 %res
}
define i1 @ula_swap12(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ula_swap12:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %c, %a
%l1 = icmp ugt i64 %c, %b
%res = and i1 %l0, %l1
ret i1 %res
}
; 4 patterns below will be converted to umax+greater
; (greater will be converted to setult somehow)
define i1 @ugo(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ugo:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %a, %c
%l1 = icmp ugt i64 %b, %c
%res = or i1 %l0, %l1
ret i1 %res
}
define i1 @ugo_swap1(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ugo_swap1:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: ret
%l0 = icmp ult i64 %c, %a
%l1 = icmp ugt i64 %b, %c
%res = or i1 %l0, %l1
ret i1 %res
}
define i1 @ugo_swap2(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ugo_swap2:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %a, %c
%l1 = icmp ult i64 %c, %b
%res = or i1 %l0, %l1
ret i1 %res
}
define i1 @ugo_swap12(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ugo_swap12:
; CHECK: # %bb.0:
; CHECK-NEXT: maxu a1, a1, a2
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: ret
%l0 = icmp ult i64 %c, %a
%l1 = icmp ult i64 %c, %b
%res = or i1 %l0, %l1
ret i1 %res
}
; Pattern below will be converted to umin+greater or equal
; (greater will be converted to setult somehow)
define i1 @ugea(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: ugea:
; CHECK: # %bb.0:
; CHECK-NEXT: minu a1, a1, a2
; CHECK-NEXT: sltu a0, a1, a0
; CHECK-NEXT: xori a0, a0, 1
; CHECK-NEXT: ret
%l0 = icmp uge i64 %a, %c
%l1 = icmp uge i64 %b, %c
%res = and i1 %l0, %l1
ret i1 %res
}
; Pattern below will be converted to umin+greater
; (greater will be converted to setult somehow)
define i1 @uga(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: uga:
; CHECK: # %bb.0:
; CHECK-NEXT: minu a1, a1, a2
; CHECK-NEXT: sltu a0, a0, a1
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %a, %c
%l1 = icmp ugt i64 %b, %c
%res = and i1 %l0, %l1
ret i1 %res
}
; Patterns below will be converted to smax+less.
; Sign check.
define i1 @sla(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: sla:
; CHECK: # %bb.0:
; CHECK-NEXT: max a1, a1, a2
; CHECK-NEXT: slt a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp slt i64 %a, %c
%l1 = icmp slt i64 %b, %c
%res = and i1 %l0, %l1
ret i1 %res
}
; Negative test
; Float check.
define i1 @flo(float %c, float %a, float %b) {
; CHECK-RV64I-LABEL: flo:
; CHECK-RV64I: # %bb.0:
; CHECK-RV64I-NEXT: addi sp, sp, -32
; CHECK-RV64I-NEXT: .cfi_def_cfa_offset 32
; CHECK-RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-RV64I-NEXT: .cfi_offset ra, -8
; CHECK-RV64I-NEXT: .cfi_offset s0, -16
; CHECK-RV64I-NEXT: .cfi_offset s1, -24
; CHECK-RV64I-NEXT: .cfi_offset s2, -32
; CHECK-RV64I-NEXT: mv s0, a2
; CHECK-RV64I-NEXT: mv s1, a0
; CHECK-RV64I-NEXT: mv a0, a1
; CHECK-RV64I-NEXT: mv a1, s1
; CHECK-RV64I-NEXT: call __gesf2@plt
; CHECK-RV64I-NEXT: mv s2, a0
; CHECK-RV64I-NEXT: mv a0, s0
; CHECK-RV64I-NEXT: mv a1, s1
; CHECK-RV64I-NEXT: call __gesf2@plt
; CHECK-RV64I-NEXT: min a0, s2, a0
; CHECK-RV64I-NEXT: slti a0, a0, 0
; CHECK-RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-RV64I-NEXT: addi sp, sp, 32
; CHECK-RV64I-NEXT: ret
;
; CHECK-RV64IF-LABEL: flo:
; CHECK-RV64IF: # %bb.0:
; CHECK-RV64IF-NEXT: fle.s a0, fa0, fa1
; CHECK-RV64IF-NEXT: fle.s a1, fa0, fa2
; CHECK-RV64IF-NEXT: and a0, a0, a1
; CHECK-RV64IF-NEXT: xori a0, a0, 1
; CHECK-RV64IF-NEXT: ret
%l0 = fcmp ult float %a, %c
%l1 = fcmp ult float %b, %c
%res = or i1 %l0, %l1
ret i1 %res
}
; Negative test
; Double check.
define i1 @dlo(double %c, double %a, double %b) {
; CHECK-LABEL: dlo:
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: .cfi_offset s2, -32
; CHECK-NEXT: mv s0, a2
; CHECK-NEXT: mv s1, a0
; CHECK-NEXT: mv a0, a1
; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __gedf2@plt
; CHECK-NEXT: mv s2, a0
; CHECK-NEXT: mv a0, s0
; CHECK-NEXT: mv a1, s1
; CHECK-NEXT: call __gedf2@plt
; CHECK-NEXT: min a0, s2, a0
; CHECK-NEXT: slti a0, a0, 0
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%l0 = fcmp ult double %a, %c
%l1 = fcmp ult double %b, %c
%res = or i1 %l0, %l1
ret i1 %res
}
; Negative test
; More than one user
define i1 @multi_user(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: multi_user:
; CHECK: # %bb.0:
; CHECK-NEXT: sltu a1, a1, a0
; CHECK-NEXT: sltu a0, a2, a0
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ugt i64 %c, %a
%l1 = icmp ult i64 %b, %c
%res = or i1 %l0, %l1
%out = and i1 %l0, %res
ret i1 %out
}
; Negative test
; No same comparations
define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
; CHECK-LABEL: no_same_ops:
; CHECK: # %bb.0:
; CHECK-NEXT: sltu a1, a0, a1
; CHECK-NEXT: sltu a0, a2, a0
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: ret
%l0 = icmp ult i64 %c, %a
%l1 = icmp ugt i64 %c, %b
%res = or i1 %l0, %l1
ret i1 %res
}
|
