File: expand-pseudos.mir

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llvm-toolchain-17 1%3A17.0.6-22
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -run-pass=arm-pseudo -verify-machineinstrs %s -o - | FileCheck %s
--- |
  target triple = "thumbv7---gnueabi"

  @var = global i32 0
  define i32 @test1(i32 %x) {
  entry:
    unreachable
  }
...
---
name:            test1
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r0_r1', virtual-reg: '' }
body:             |
  bb.0.entry:
    liveins: $r0, $r0_r1

    ; CHECK-LABEL: name: test1
    ; CHECK: liveins: $r0, $r0_r1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: $r0 = t2LDRpci @var, 14 /* CC::al */, $noreg, implicit-def $r0_r1
    ; CHECK-NEXT: $r0 = tPICADD $r0, 0, implicit-def $r0_r1
    ; CHECK-NEXT: BX_RET 14 /* CC::al */, $noreg, implicit $r0
    $r0 = t2LDRpci_pic @var, 0, implicit-def $r0_r1
    BX_RET 14, $noreg, implicit $r0

...