1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s
declare <256 x double> @llvm.masked.gather.v256f64.v256p0(<256 x ptr> %0, i32 immarg %1, <256 x i1> %2, <256 x double> %3) #0
; Function Attrs: nounwind
define fastcc <256 x double> @vec_mgather_v256f64(<256 x ptr> %P, <256 x i1> %M) {
; CHECK-LABEL: vec_mgather_v256f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vgt %v0, %v0, 0, 0
; CHECK-NEXT: b.l.t (, %s10)
%r = call <256 x double> @llvm.masked.gather.v256f64.v256p0(<256 x ptr> %P, i32 4, <256 x i1> %M, <256 x double> undef)
ret <256 x double> %r
}
; Function Attrs: nounwind
define fastcc <256 x double> @vec_mgather_pt_v256f64(<256 x ptr> %P, <256 x double> %PT, <256 x i1> %M) {
; CHECK-LABEL: vec_mgather_pt_v256f64:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vgt %v2, %v0, 0, 0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmrg %v0, %v1, %v2, %vm0
; CHECK-NEXT: b.l.t (, %s10)
%r = call <256 x double> @llvm.masked.gather.v256f64.v256p0(<256 x ptr> %P, i32 4, <256 x i1> %M, <256 x double> %PT)
ret <256 x double> %r
}
declare <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> %0, i32 immarg %1, <256 x i1> %2, <256 x float> %3) #0
; Function Attrs: nounwind
define fastcc <256 x float> @vec_mgather_v256f32(<256 x ptr> %P, <256 x i1> %M) {
; CHECK-LABEL: vec_mgather_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vgtu %v0, %v0, 0, 0
; CHECK-NEXT: b.l.t (, %s10)
%r = call <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> %P, i32 4, <256 x i1> %M, <256 x float> undef)
ret <256 x float> %r
}
; Function Attrs: nounwind
define fastcc <256 x float> @vec_mgather_pt_v256f32(<256 x ptr> %P, <256 x float> %PT, <256 x i1> %M) {
; CHECK-LABEL: vec_mgather_pt_v256f32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vgtu %v2, %v0, 0, 0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmrg %v0, %v1, %v2, %vm0
; CHECK-NEXT: b.l.t (, %s10)
%r = call <256 x float> @llvm.masked.gather.v256f32.v256p0(<256 x ptr> %P, i32 4, <256 x i1> %M, <256 x float> %PT)
ret <256 x float> %r
}
declare <256 x i32> @llvm.masked.gather.v256i32.v256p0(<256 x ptr> %0, i32 immarg %1, <256 x i1> %2, <256 x i32> %3) #0
; Function Attrs: nounwind
define fastcc <256 x i32> @vec_mgather_v256i32(<256 x ptr> %P, <256 x i1> %M) {
; CHECK-LABEL: vec_mgather_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vgtl.zx %v0, %v0, 0, 0
; CHECK-NEXT: b.l.t (, %s10)
%r = call <256 x i32> @llvm.masked.gather.v256i32.v256p0(<256 x ptr> %P, i32 4, <256 x i1> %M, <256 x i32> undef)
ret <256 x i32> %r
}
; Function Attrs: nounwind
define fastcc <256 x i32> @vec_mgather_pt_v256i32(<256 x ptr> %P, <256 x i32> %PT, <256 x i1> %M) {
; CHECK-LABEL: vec_mgather_pt_v256i32:
; CHECK: # %bb.0:
; CHECK-NEXT: lea %s0, 256
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vgtl.zx %v2, %v0, 0, 0
; CHECK-NEXT: lea %s16, 256
; CHECK-NEXT: lvl %s16
; CHECK-NEXT: vor %v0, (0)1, %v1
; CHECK-NEXT: lvl %s0
; CHECK-NEXT: vmrg %v0, %v1, %v2, %vm0
; CHECK-NEXT: b.l.t (, %s10)
%r = call <256 x i32> @llvm.masked.gather.v256i32.v256p0(<256 x ptr> %P, i32 4, <256 x i1> %M, <256 x i32> %PT)
ret <256 x i32> %r
}
attributes #0 = { argmemonly nounwind readonly willreturn }
|
