1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
declare {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
; fold (sadd x, 0) -> x
define i32 @combine_sadd_zero(i32 %a0, i32 %a1) {
; SSE-LABEL: combine_sadd_zero:
; SSE: # %bb.0:
; SSE-NEXT: movl %edi, %eax
; SSE-NEXT: retq
;
; AVX-LABEL: combine_sadd_zero:
; AVX: # %bb.0:
; AVX-NEXT: movl %edi, %eax
; AVX-NEXT: retq
%1 = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %a0, i32 zeroinitializer)
%2 = extractvalue {i32, i1} %1, 0
%3 = extractvalue {i32, i1} %1, 1
%4 = select i1 %3, i32 %a1, i32 %2
ret i32 %4
}
define <4 x i32> @combine_vec_sadd_zero(<4 x i32> %a0, <4 x i32> %a1) {
; SSE-LABEL: combine_vec_sadd_zero:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_sadd_zero:
; AVX: # %bb.0:
; AVX-NEXT: retq
%1 = call {<4 x i32>, <4 x i1>} @llvm.sadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
ret <4 x i32> %4
}
; fold (uadd x, 0) -> x
define i32 @combine_uadd_zero(i32 %a0, i32 %a1) {
; SSE-LABEL: combine_uadd_zero:
; SSE: # %bb.0:
; SSE-NEXT: movl %edi, %eax
; SSE-NEXT: retq
;
; AVX-LABEL: combine_uadd_zero:
; AVX: # %bb.0:
; AVX-NEXT: movl %edi, %eax
; AVX-NEXT: retq
%1 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %a0, i32 zeroinitializer)
%2 = extractvalue {i32, i1} %1, 0
%3 = extractvalue {i32, i1} %1, 1
%4 = select i1 %3, i32 %a1, i32 %2
ret i32 %4
}
define <4 x i32> @combine_vec_uadd_zero(<4 x i32> %a0, <4 x i32> %a1) {
; SSE-LABEL: combine_vec_uadd_zero:
; SSE: # %bb.0:
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_uadd_zero:
; AVX: # %bb.0:
; AVX-NEXT: retq
%1 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> zeroinitializer)
%2 = extractvalue {<4 x i32>, <4 x i1>} %1, 0
%3 = extractvalue {<4 x i32>, <4 x i1>} %1, 1
%4 = select <4 x i1> %3, <4 x i32> %a1, <4 x i32> %2
ret <4 x i32> %4
}
; fold (uadd (xor a, -1), 1) -> (usub 0, a) and flip carry
define i32 @combine_uadd_not(i32 %a0, i32 %a1) {
; SSE-LABEL: combine_uadd_not:
; SSE: # %bb.0:
; SSE-NEXT: movl %edi, %eax
; SSE-NEXT: negl %eax
; SSE-NEXT: cmovael %esi, %eax
; SSE-NEXT: retq
;
; AVX-LABEL: combine_uadd_not:
; AVX: # %bb.0:
; AVX-NEXT: movl %edi, %eax
; AVX-NEXT: negl %eax
; AVX-NEXT: cmovael %esi, %eax
; AVX-NEXT: retq
%1 = xor i32 %a0, -1
%2 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 1)
%3 = extractvalue {i32, i1} %2, 0
%4 = extractvalue {i32, i1} %2, 1
%5 = select i1 %4, i32 %a1, i32 %3
ret i32 %5
}
define <4 x i32> @combine_vec_uadd_not(<4 x i32> %a0, <4 x i32> %a1) {
; SSE-LABEL: combine_vec_uadd_not:
; SSE: # %bb.0:
; SSE-NEXT: pxor %xmm2, %xmm2
; SSE-NEXT: psubd %xmm0, %xmm2
; SSE-NEXT: movdqa {{.*#+}} xmm0 = [1,1,1,1]
; SSE-NEXT: pmaxud %xmm2, %xmm0
; SSE-NEXT: pcmpeqd %xmm2, %xmm0
; SSE-NEXT: blendvps %xmm0, %xmm2, %xmm1
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_uadd_not:
; AVX: # %bb.0:
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX-NEXT: vpsubd %xmm0, %xmm2, %xmm0
; AVX-NEXT: vpbroadcastd {{.*#+}} xmm2 = [1,1,1,1]
; AVX-NEXT: vpmaxud %xmm2, %xmm0, %xmm2
; AVX-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm2
; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
%1 = xor <4 x i32> %a0, <i32 -1, i32 -1, i32 -1, i32 -1>
%2 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)
%3 = extractvalue {<4 x i32>, <4 x i1>} %2, 0
%4 = extractvalue {<4 x i32>, <4 x i1>} %2, 1
%5 = select <4 x i1> %4, <4 x i32> %a1, <4 x i32> %3
ret <4 x i32> %5
}
; if uaddo never overflows, replace with add
define i32 @combine_uadd_no_overflow(i32 %a0, i32 %a1, i32 %a2) {
; SSE-LABEL: combine_uadd_no_overflow:
; SSE: # %bb.0:
; SSE-NEXT: # kill: def $edx killed $edx def $rdx
; SSE-NEXT: # kill: def $esi killed $esi def $rsi
; SSE-NEXT: shrl $16, %esi
; SSE-NEXT: shrl $16, %edx
; SSE-NEXT: leal (%rdx,%rsi), %eax
; SSE-NEXT: retq
;
; AVX-LABEL: combine_uadd_no_overflow:
; AVX: # %bb.0:
; AVX-NEXT: # kill: def $edx killed $edx def $rdx
; AVX-NEXT: # kill: def $esi killed $esi def $rsi
; AVX-NEXT: shrl $16, %esi
; AVX-NEXT: shrl $16, %edx
; AVX-NEXT: leal (%rdx,%rsi), %eax
; AVX-NEXT: retq
%1 = lshr i32 %a1, 16
%2 = lshr i32 %a2, 16
%3 = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %1, i32 %2)
%4 = extractvalue {i32, i1} %3, 0
%5 = extractvalue {i32, i1} %3, 1
%6 = select i1 %5, i32 %a2, i32 %4
ret i32 %4
}
define <4 x i32> @combine_vec_uadd_no_overflow(<4 x i32> %a0, <4 x i32> %a1, <4 x i32> %a2) {
; SSE-LABEL: combine_vec_uadd_no_overflow:
; SSE: # %bb.0:
; SSE-NEXT: movdqa %xmm2, %xmm0
; SSE-NEXT: psrld $16, %xmm1
; SSE-NEXT: psrld $16, %xmm0
; SSE-NEXT: paddd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: combine_vec_uadd_no_overflow:
; AVX: # %bb.0:
; AVX-NEXT: vpsrld $16, %xmm1, %xmm0
; AVX-NEXT: vpsrld $16, %xmm2, %xmm1
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = lshr <4 x i32> %a1, <i32 16, i32 16, i32 16, i32 16>
%2 = lshr <4 x i32> %a2, <i32 16, i32 16, i32 16, i32 16>
%3 = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %1, <4 x i32> %2)
%4 = extractvalue {<4 x i32>, <4 x i1>} %3, 0
%5 = extractvalue {<4 x i32>, <4 x i1>} %3, 1
%6 = select <4 x i1> %5, <4 x i32> %a2, <4 x i32> %4
ret <4 x i32> %4
}
|
