1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes='loop-mssa(indvars,loop-rotate)' -verify-scev -S %s | FileCheck %s
define void @pr59534(i16 %c.0, ptr %A) {
; CHECK-LABEL: @pr59534(
; CHECK-NEXT: entry:
; CHECK-NEXT: br label [[LOOP_HEADER:%.*]]
; CHECK: loop.header:
; CHECK-NEXT: [[C_1:%.*]] = icmp ne i16 [[C_0:%.*]], 0
; CHECK-NEXT: br i1 [[C_1]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
; CHECK: if.then:
; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[A:%.*]], align 1
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[L]], 0
; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i16
; CHECK-NEXT: store i16 [[CONV]], ptr [[A]], align 2
; CHECK-NEXT: br label [[IF_END]]
; CHECK: if.end:
; CHECK-NEXT: br i1 false, label [[LOOP_HEADER]], label [[EXIT:%.*]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop.header
loop.header:
%e.0 = phi i32 [ 0, %entry ], [ 1, %loop.latch ]
%c.1 = icmp ne i16 %c.0, 0
br i1 %c.1, label %if.then, label %if.end
if.then:
%l = load i32, ptr %A, align 1
%cmp = icmp sgt i32 %l, %e.0
%conv = zext i1 %cmp to i16
store i16 %conv, ptr %A
br label %if.end
if.end:
br i1 false, label %loop.latch, label %exit
loop.latch:
br label %loop.header
exit:
ret void
}
|
