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|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature
; RUN: opt -passes="default<O1>" -S < %s | FileCheck --check-prefixes=O1 %s
; RUN: opt -passes="default<O2>" -S < %s | FileCheck --check-prefixes=O23 %s
; RUN: opt -passes="default<O3>" -S < %s | FileCheck --check-prefixes=O23 %s
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
%class.FloatVecPair = type { %class.HomemadeVector, %class.HomemadeVector }
%class.HomemadeVector = type <{ ptr, i32, [4 x i8] }>
%class.HomemadeVector.0 = type <{ ptr, i32, [4 x i8] }>
$_ZN12FloatVecPair6vecIncEv = comdat any
define dso_local void @_Z13vecIncFromPtrP12FloatVecPair(ptr %FVP) {
; O1-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair
; O1-SAME: (ptr nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O1-NEXT: entry:
; O1-NEXT: [[VSRC23_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], ptr [[FVP]], i64 0, i32 1
; O1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VSRC23_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
; O1-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], ptr [[TMP0]], i64 undef, i32 1
; O1-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]]
; O1-NEXT: [[CMP56_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
; O1-NEXT: br i1 [[CMP56_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
; O1: for.body7.lr.ph.i:
; O1-NEXT: [[ARRAYIDX_I_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP0]], i64 undef
; O1-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX_I_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
; O1-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 undef
; O1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[FVP]], align 8, !tbaa [[TBAA0]]
; O1-NEXT: [[ARRAYIDX_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP3]], i64 undef
; O1-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX_I4_I]], align 8, !tbaa [[TBAA8]]
; O1-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 undef
; O1-NEXT: br label [[FOR_BODY7_I:%.*]]
; O1: for.body7.i:
; O1-NEXT: [[J_07_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ]
; O1-NEXT: [[TMP5:%.*]] = load float, ptr [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9:![0-9]+]]
; O1-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
; O1-NEXT: [[ADD_I:%.*]] = fadd float [[TMP5]], [[TMP6]]
; O1-NEXT: store float [[ADD_I]], ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
; O1-NEXT: [[INC_I]] = add nuw i32 [[J_07_I]], 1
; O1-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
; O1-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]]
; O1: _ZN12FloatVecPair6vecIncEv.exit:
; O1-NEXT: ret void
;
; O23-LABEL: define {{[^@]+}}@_Z13vecIncFromPtrP12FloatVecPair
; O23-SAME: (ptr nocapture readonly [[FVP:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; O23-NEXT: entry:
; O23-NEXT: [[VSRC23_I:%.*]] = getelementptr inbounds [[CLASS_FLOATVECPAIR:%.*]], ptr [[FVP]], i64 0, i32 1
; O23-NEXT: [[TMP0:%.*]] = load ptr, ptr [[VSRC23_I]], align 8, !tbaa [[TBAA0:![0-9]+]]
; O23-NEXT: [[SIZE4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0:%.*]], ptr [[TMP0]], i64 undef, i32 1
; O23-NEXT: [[TMP1:%.*]] = load i32, ptr [[SIZE4_I]], align 8, !tbaa [[TBAA6:![0-9]+]]
; O23-NEXT: [[CMP56_NOT_I:%.*]] = icmp eq i32 [[TMP1]], 0
; O23-NEXT: br i1 [[CMP56_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT:%.*]], label [[FOR_BODY7_LR_PH_I:%.*]]
; O23: for.body7.lr.ph.i:
; O23-NEXT: [[ARRAYIDX_I_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP0]], i64 undef
; O23-NEXT: [[TMP2:%.*]] = load ptr, ptr [[ARRAYIDX_I_I]], align 8, !tbaa [[TBAA8:![0-9]+]]
; O23-NEXT: [[ARRAYIDX_I3_I:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 undef
; O23-NEXT: [[TMP3:%.*]] = load ptr, ptr [[FVP]], align 8, !tbaa [[TBAA0]]
; O23-NEXT: [[ARRAYIDX_I4_I:%.*]] = getelementptr inbounds [[CLASS_HOMEMADEVECTOR_0]], ptr [[TMP3]], i64 undef
; O23-NEXT: [[TMP4:%.*]] = load ptr, ptr [[ARRAYIDX_I4_I]], align 8, !tbaa [[TBAA8]]
; O23-NEXT: [[ARRAYIDX_I5_I:%.*]] = getelementptr inbounds float, ptr [[TMP4]], i64 undef
; O23-NEXT: [[DOTPRE_I:%.*]] = load float, ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9:![0-9]+]]
; O23-NEXT: br label [[FOR_BODY7_I:%.*]]
; O23: for.body7.i:
; O23-NEXT: [[TMP5:%.*]] = phi float [ [[DOTPRE_I]], [[FOR_BODY7_LR_PH_I]] ], [ [[ADD_I:%.*]], [[FOR_BODY7_I]] ]
; O23-NEXT: [[J_07_I:%.*]] = phi i32 [ 0, [[FOR_BODY7_LR_PH_I]] ], [ [[INC_I:%.*]], [[FOR_BODY7_I]] ]
; O23-NEXT: [[TMP6:%.*]] = load float, ptr [[ARRAYIDX_I3_I]], align 4, !tbaa [[TBAA9]]
; O23-NEXT: [[ADD_I]] = fadd float [[TMP5]], [[TMP6]]
; O23-NEXT: store float [[ADD_I]], ptr [[ARRAYIDX_I5_I]], align 4, !tbaa [[TBAA9]]
; O23-NEXT: [[INC_I]] = add nuw i32 [[J_07_I]], 1
; O23-NEXT: [[EXITCOND_NOT_I:%.*]] = icmp eq i32 [[INC_I]], [[TMP1]]
; O23-NEXT: br i1 [[EXITCOND_NOT_I]], label [[_ZN12FLOATVECPAIR6VECINCEV_EXIT]], label [[FOR_BODY7_I]], !llvm.loop [[LOOP11:![0-9]+]]
; O23: _ZN12FloatVecPair6vecIncEv.exit:
; O23-NEXT: ret void
;
entry:
%FVP.addr = alloca ptr, align 8
store ptr %FVP, ptr %FVP.addr, align 8, !tbaa !0
%0 = load ptr, ptr %FVP.addr, align 8, !tbaa !0
call void @_ZN12FloatVecPair6vecIncEv(ptr %0)
ret void
}
define linkonce_odr dso_local void @_ZN12FloatVecPair6vecIncEv(ptr %this) comdat align 2 {
entry:
%this.addr = alloca ptr, align 8
%j = alloca i32, align 4
store ptr %this, ptr %this.addr, align 8, !tbaa !0
%this1 = load ptr, ptr %this.addr, align 8
br label %for.cond
for.cond: ; preds = %entry
br label %for.body
for.body: ; preds = %for.cond
store i32 0, ptr %j, align 4, !tbaa !4
br label %for.cond2
for.cond2: ; preds = %for.inc, %for.body
%0 = load i32, ptr %j, align 4, !tbaa !4
%Vsrc23 = getelementptr inbounds %class.FloatVecPair, ptr %this1, i32 0, i32 1
%call = call ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %Vsrc23)
%size4 = getelementptr inbounds %class.HomemadeVector.0, ptr %call, i32 0, i32 1
%1 = load i32, ptr %size4, align 8, !tbaa !6
%cmp5 = icmp ult i32 %0, %1
br i1 %cmp5, label %for.body7, label %for.cond.cleanup6
for.cond.cleanup6: ; preds = %for.cond2
ret void
for.body7: ; preds = %for.cond2
%Vsrc28 = getelementptr inbounds %class.FloatVecPair, ptr %this1, i32 0, i32 1
%call9 = call ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %Vsrc28)
%call10 = call ptr @_ZN14HomemadeVectorIfLj8EEixEj(ptr %call9)
%2 = load float, ptr %call10, align 4, !tbaa !8
%call11 = call ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %this1)
%call12 = call ptr @_ZN14HomemadeVectorIfLj8EEixEj(ptr %call11)
%3 = load float, ptr %call12, align 4, !tbaa !8
%add = fadd float %3, %2
store float %add, ptr %call12, align 4, !tbaa !8
br label %for.inc
for.inc: ; preds = %for.body7
%4 = load i32, ptr %j, align 4, !tbaa !4
%inc = add i32 %4, 1
store i32 %inc, ptr %j, align 4, !tbaa !4
br label %for.cond2, !llvm.loop !10
}
define linkonce_odr dso_local ptr @_ZN14HomemadeVectorIS_IfLj8EELj8EEixEj(ptr %this) align 2 {
entry:
%this.addr = alloca ptr, align 8
store ptr %this, ptr %this.addr, align 8, !tbaa !0
%this1 = load ptr, ptr %this.addr, align 8
%0 = load ptr, ptr %this1, align 8, !tbaa !12
%arrayidx = getelementptr inbounds %class.HomemadeVector.0, ptr %0, i64 undef
ret ptr %arrayidx
}
define linkonce_odr dso_local ptr @_ZN14HomemadeVectorIfLj8EEixEj(ptr %this) align 2 {
entry:
%this.addr = alloca ptr, align 8
store ptr %this, ptr %this.addr, align 8, !tbaa !0
%this1 = load ptr, ptr %this.addr, align 8
%0 = load ptr, ptr %this1, align 8, !tbaa !14
%arrayidx = getelementptr inbounds float, ptr %0, i64 undef
ret ptr %arrayidx
}
!0 = !{!1, !1, i64 0}
!1 = !{!"any pointer", !2, i64 0}
!2 = !{!"omnipotent char", !3, i64 0}
!3 = !{!"Simple C++ TBAA"}
!4 = !{!5, !5, i64 0}
!5 = !{!"int", !2, i64 0}
!6 = !{!7, !5, i64 8}
!7 = !{!"_ZTS14HomemadeVectorIfLj8EE", !1, i64 0, !5, i64 8}
!8 = !{!9, !9, i64 0}
!9 = !{!"float", !2, i64 0}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
!12 = !{!13, !1, i64 0}
!13 = !{!"_ZTS14HomemadeVectorIS_IfLj8EELj8EE", !1, i64 0, !5, i64 8}
!14 = !{!7, !1, i64 0}
|
