File: reduce-register-uses-generic.mir

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# REQUIRES: amdgpu-registered-target
# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=register-uses -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --match-full-lines --check-prefix=RESULT %s < %t

# Generic instructions should not have undef set on operands
# CHECK-INTERESTINGNESS: G_ADD

# RESULT: %1:vreg_64(s64) = IMPLICIT_DEF
# RESULT: %add:_(s64) = G_ADD %1, %1

---
name: func
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3

    %0:vgpr(s32) = G_IMPLICIT_DEF
    %1:vreg_64(s64) = IMPLICIT_DEF
    %add:_(s64) = G_ADD %1, %1
    %ptr:_(p1) = G_IMPLICIT_DEF
    G_STORE %0(s32), %ptr(p1) :: (store (s32), addrspace 1)
    S_ENDPGM 0, implicit %add(s64), implicit %1(s64)

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