1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
|
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 -ppc-disable-perfect-shuffle=false | not grep vperm
; TODO: Fix this case when disabling perfect shuffle
define <4 x float> @test_uu72(ptr %P1, ptr %P2) {
%V1 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, ptr %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_30u5(ptr %P1, ptr %P2) {
%V1 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, ptr %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_3u73(ptr %P1, ptr %P2) {
%V1 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, ptr %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_3774(ptr %P1, ptr %P2) {
%V1 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, ptr %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
define <4 x float> @test_4450(ptr %P1, ptr %P2) {
%V1 = load <4 x float>, ptr %P1 ; <<4 x float>> [#uses=1]
%V2 = load <4 x float>, ptr %P2 ; <<4 x float>> [#uses=1]
%V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; <<4 x float>> [#uses=1]
ret <4 x float> %V3
}
|
