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|
Index: llvm-toolchain-18-18.1.8/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- llvm-toolchain-18-18.1.8.orig/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ llvm-toolchain-18-18.1.8/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -2168,7 +2168,8 @@ void SelectionDAGLegalize::ExpandFPLibCa
Results.push_back(Tmp.first);
Results.push_back(Tmp.second);
} else {
- SDValue Tmp = ExpandLibCall(LC, Node, false).first;
+ bool IsSignedArgument = Node->getOpcode() == ISD::FLDEXP;
+ SDValue Tmp = ExpandLibCall(LC, Node, IsSignedArgument).first;
Results.push_back(Tmp);
}
}
Index: llvm-toolchain-18-18.1.8/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll
===================================================================
--- llvm-toolchain-18-18.1.8.orig/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll
+++ llvm-toolchain-18-18.1.8/llvm/test/CodeGen/PowerPC/ldexp-libcall.ll
@@ -10,7 +10,7 @@ define float @call_ldexpf(float %a, i32
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
-; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: extsw r4, r4
; CHECK-NEXT: bl ldexpf
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
@@ -29,7 +29,7 @@ define double @call_ldexp(double %a, i32
; CHECK-NEXT: std r0, 48(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
-; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: extsw r4, r4
; CHECK-NEXT: bl ldexp
; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 32
Index: llvm-toolchain-18-18.1.8/llvm/test/CodeGen/PowerPC/ldexp.ll
===================================================================
--- llvm-toolchain-18-18.1.8.orig/llvm/test/CodeGen/PowerPC/ldexp.ll
+++ llvm-toolchain-18-18.1.8/llvm/test/CodeGen/PowerPC/ldexp.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s | FileCheck %s
+; XFAIL: *
define float @ldexp_f32(i8 zeroext %x) {
; CHECK-LABEL: ldexp_f32:
@@ -59,22 +60,24 @@ define <2 x float> @ldexp_v2f32(<2 x flo
; CHECK-NEXT: .cfi_offset v29, -48
; CHECK-NEXT: .cfi_offset v30, -32
; CHECK-NEXT: .cfi_offset v31, -16
-; CHECK-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-NEXT: li r3, 0
+; CHECK-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-NEXT: stxv v29, 32(r1) # 16-byte Folded Spill
; CHECK-NEXT: xscvspdpn f1, vs0
-; CHECK-NEXT: vextuwrx r4, r3, v3
+; CHECK-NEXT: vextuwrx r3, r3, v3
; CHECK-NEXT: stxv v30, 48(r1) # 16-byte Folded Spill
; CHECK-NEXT: stxv v31, 64(r1) # 16-byte Folded Spill
+; CHECK-NEXT: extsw r4, r3
; CHECK-NEXT: vmr v31, v3
; CHECK-NEXT: vmr v30, v2
; CHECK-NEXT: bl ldexpf
; CHECK-NEXT: nop
-; CHECK-NEXT: xxswapd vs0, v30
; CHECK-NEXT: li r3, 4
+; CHECK-NEXT: xxswapd vs0, v30
; CHECK-NEXT: xscvdpspn v29, f1
; CHECK-NEXT: xscvspdpn f1, vs0
-; CHECK-NEXT: vextuwrx r4, r3, v31
+; CHECK-NEXT: vextuwrx r3, r3, v31
+; CHECK-NEXT: extsw r4, r3
; CHECK-NEXT: bl ldexpf
; CHECK-NEXT: nop
; CHECK-NEXT: xscvdpspn vs0, f1
@@ -160,7 +163,7 @@ define half @ldexp_f16(half %arg0, i32 %
; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: xscvdphp f0, f1
-; CHECK-NEXT: clrldi r4, r4, 32
+; CHECK-NEXT: extsw r4, r4
; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrlwi r3, r3, 16
; CHECK-NEXT: mtfprwz f0, r3
Index: llvm-toolchain-18-18.1.8/llvm/test/CodeGen/PowerPC/negative-integer-fp-libcall.ll
===================================================================
--- /dev/null
+++ llvm-toolchain-18-18.1.8/llvm/test/CodeGen/PowerPC/negative-integer-fp-libcall.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -O1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
+
+; Test that a negative parameter smaller than 64 bits (e.g., int)
+; is correctly implemented with sign-extension when passed to
+; a floating point libcall.
+
+define double @ldexp_test(ptr %a, ptr %b) nounwind {
+; CHECK-LABEL: ldexp_test:
+; CHECK: # %bb.0:
+; CHECK-NEXT: mflr 0
+; CHECK-NEXT: stdu 1, -112(1)
+; CHECK-NEXT: std 0, 128(1)
+; CHECK-NEXT: lfd 1, 0(3)
+; CHECK-NEXT: lwa 4, 0(4)
+; CHECK-NEXT: bl ldexp
+; CHECK-NEXT: nop
+; CHECK-NEXT: addi 1, 1, 112
+; CHECK-NEXT: ld 0, 16(1)
+; CHECK-NEXT: mtlr 0
+; CHECK-NEXT: blr
+ %base = load double, ptr %a
+ %exp = load i32, ptr %b
+ %call = call double @llvm.ldexp.f64.i32(double %base, i32 signext %exp)
+ ret double %call
+}
Index: llvm-toolchain-18-18.1.8/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
===================================================================
--- llvm-toolchain-18-18.1.8.orig/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
+++ llvm-toolchain-18-18.1.8/llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
@@ -406,13 +406,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-SSE-NEXT: subq $72, %rsp
; CHECK-SSE-NEXT: .cfi_def_cfa_offset 80
; CHECK-SSE-NEXT: movdqa %xmm0, (%rsp) # 16-byte Spill
-; CHECK-SSE-NEXT: pextrw $7, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $7, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
; CHECK-SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-SSE-NEXT: pextrw $6, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $6, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
@@ -420,13 +422,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-SSE-NEXT: pextrw $5, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $5, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
; CHECK-SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-SSE-NEXT: pextrw $4, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $4, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
@@ -436,13 +440,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-SSE-NEXT: pextrw $3, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $3, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
; CHECK-SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-SSE-NEXT: pextrw $2, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $2, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
@@ -450,14 +456,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-SSE-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-SSE-NEXT: pextrw $1, %xmm0, %edi
+; CHECK-SSE-NEXT: pextrw $1, %xmm0, %eax
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
; CHECK-SSE-NEXT: movaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-SSE-NEXT: movdqa (%rsp), %xmm0 # 16-byte Reload
; CHECK-SSE-NEXT: movd %xmm0, %eax
-; CHECK-SSE-NEXT: movzwl %ax, %edi
+; CHECK-SSE-NEXT: movswl %ax, %edi
; CHECK-SSE-NEXT: movd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-SSE-NEXT: callq ldexpf@PLT
; CHECK-SSE-NEXT: callq __truncsfhf2@PLT
@@ -476,13 +483,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX2-NEXT: subq $72, %rsp
; CHECK-AVX2-NEXT: .cfi_def_cfa_offset 80
; CHECK-AVX2-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
-; CHECK-AVX2-NEXT: vpextrw $7, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $7, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
; CHECK-AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX2-NEXT: vpextrw $6, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $6, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
@@ -490,13 +499,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX2-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX2-NEXT: vpextrw $5, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $5, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
; CHECK-AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX2-NEXT: vpextrw $4, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $4, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
@@ -506,13 +517,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX2-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX2-NEXT: vpextrw $3, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $3, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
; CHECK-AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX2-NEXT: vpextrw $2, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $2, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
@@ -520,14 +533,15 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX2-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX2-NEXT: vpextrw $1, %xmm0, %edi
+; CHECK-AVX2-NEXT: vpextrw $1, %xmm0, %eax
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
; CHECK-AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX2-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
; CHECK-AVX2-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX2-NEXT: movzwl %ax, %edi
+; CHECK-AVX2-NEXT: movswl %ax, %edi
; CHECK-AVX2-NEXT: vmovd {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX2-NEXT: callq ldexpf@PLT
; CHECK-AVX2-NEXT: callq __truncsfhf2@PLT
@@ -546,7 +560,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: subq $72, %rsp
; CHECK-AVX512F-NEXT: .cfi_def_cfa_offset 80
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, (%rsp) # 16-byte Spill
-; CHECK-AVX512F-NEXT: vpextrw $7, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $7, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -554,7 +569,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $6, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $6, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -564,7 +580,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $5, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $5, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -572,7 +589,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $4, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $4, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -584,7 +602,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $3, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $3, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -592,7 +611,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $2, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $2, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -602,7 +622,8 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
-; CHECK-AVX512F-NEXT: vpextrw $1, %xmm0, %edi
+; CHECK-AVX512F-NEXT: vpextrw $1, %xmm0, %eax
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
@@ -611,7 +632,7 @@ define <8 x half> @fmul_pow2_ldexp_8xhal
; CHECK-AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill
; CHECK-AVX512F-NEXT: vmovdqa (%rsp), %xmm0 # 16-byte Reload
; CHECK-AVX512F-NEXT: vmovd %xmm0, %eax
-; CHECK-AVX512F-NEXT: movzwl %ax, %edi
+; CHECK-AVX512F-NEXT: movswl %ax, %edi
; CHECK-AVX512F-NEXT: vmovss {{.*#+}} xmm0 = [8.192E+3,0.0E+0,0.0E+0,0.0E+0]
; CHECK-AVX512F-NEXT: callq ldexpf@PLT
; CHECK-AVX512F-NEXT: vcvtps2ph $4, %xmm0, %xmm0
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