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//===- Xtensa.td - Describe the Xtensa Target Machine ------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Target-independent interfaces
//===----------------------------------------------------------------------===//
include "llvm/Target/Target.td"
//===----------------------------------------------------------------------===//
// Subtarget Features.
//===----------------------------------------------------------------------===//
def FeatureDensity : SubtargetFeature<"density", "HasDensity", "true",
"Enable Density instructions">;
def HasDensity : Predicate<"Subtarget->hasDensity()">,
AssemblerPredicate<(all_of FeatureDensity)>;
//===----------------------------------------------------------------------===//
// Xtensa supported processors.
//===----------------------------------------------------------------------===//
class Proc<string Name, list<SubtargetFeature> Features>
: Processor<Name, NoItineraries, Features>;
def : Proc<"generic", []>;
//===----------------------------------------------------------------------===//
// Register File Description
//===----------------------------------------------------------------------===//
include "XtensaRegisterInfo.td"
//===----------------------------------------------------------------------===//
// Instruction Descriptions
//===----------------------------------------------------------------------===//
include "XtensaInstrInfo.td"
def XtensaInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// Target Declaration
//===----------------------------------------------------------------------===//
def XtensaAsmParser : AsmParser {
let ShouldEmitMatchRegisterAltName = 1;
}
def XtensaInstPrinter : AsmWriter {
string AsmWriterClassName = "InstPrinter";
}
def Xtensa : Target {
let InstructionSet = XtensaInstrInfo;
let AssemblyWriters = [XtensaInstPrinter];
let AssemblyParsers = [XtensaAsmParser];
}
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