File: signext-inreg.ll

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llvm-toolchain-18 1%3A18.1.8-18
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=armv8 | FileCheck %s
; RUN: llc < %s -mtriple=armv8 -early-live-intervals -verify-machineinstrs | FileCheck %s
define <4 x i32> @test(<4 x i32> %m) {
; CHECK-LABEL: test:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    vmov d17, r2, r3
; CHECK-NEXT:    vmov d16, r0, r1
; CHECK-NEXT:    vshl.i32 q8, q8, #24
; CHECK-NEXT:    vshr.s32 q8, q8, #24
; CHECK-NEXT:    vmov r0, r1, d16
; CHECK-NEXT:    vmov r2, r3, d17
; CHECK-NEXT:    bx lr
entry:
  %shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
  %shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
  ret <4 x i32> %shr
}