File: verify-implicit-def.mir

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llvm-toolchain-18 1%3A18.1.8-18
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# REQUIRES: amdgpu-registered-target
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s

---
name: invalid_reg_sequence
tracksRegLiveness: true
body:             |
  bb.0:
    ; CHECK:   *** Bad machine code: Too few operands ***
    IMPLICIT_DEF

    ; FIXME: Error message misleading
    ; CHECK: *** Bad machine code: Explicit definition must be a register ***
    IMPLICIT_DEF 0

    ; CHECK: *** Bad machine code: Extra explicit operand on non-variadic instruction ***
    %1:vgpr_32 = IMPLICIT_DEF 0

    ; CHECK: *** Bad machine code: Extra explicit operand on non-variadic instruction ***
    ; CHECK: *** Bad machine code: Extra explicit operand on non-variadic instruction ***
    %2:vgpr_32 = IMPLICIT_DEF 0, 1

    ; CHECK: *** Bad machine code: Extra explicit operand on non-variadic instruction ***
    %3:vgpr_32 = IMPLICIT_DEF %1

    ; CHECK-NOT: Bad machine code
    %4:vgpr_32 = IMPLICIT_DEF implicit %1
...