1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
|
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfwsub_vv_f32m1_rm(vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vv_f32m1_rm(op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vf_f32m1_rm(vfloat16mf2_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vf_f32m1_rm(op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wv_f32m1_rm(vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wv_f32m1_rm(op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wf_f32m1_rm(vfloat32m1_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wf_f32m1_rm(op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vv_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vv_f32m1_rm_m(mask, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vf_f32m1_rm_m(vbool32_t mask, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vf_f32m1_rm_m(mask, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wv_f32m1_rm_m(mask, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wf_f32m1_rm_m(mask, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vv_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vv_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vf_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vf_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wv_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wv_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wf_f32m1_rm_tu(vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wf_f32m1_rm_tu(maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vv_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vf_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wv_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wf_f32m1_rm_tum(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vv_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vf_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wv_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wf_f32m1_rm_tumu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vv_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat16mf2_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_vf_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, vfloat16mf2_t op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wv_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
}
vfloat32m1_t test_vfwsub_wf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t maskedoff, vfloat32m1_t op1, _Float16 op2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfwsub_wf_f32m1_rm_mu(mask, maskedoff, op1, op2, 5, vl);
}
|
