1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
|
//===- XtensaISelDAGToDAG.cpp - A dag to dag inst selector for Xtensa -----===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the Xtensa target.
//
//===----------------------------------------------------------------------===//
#include "Xtensa.h"
#include "XtensaTargetMachine.h"
#include "XtensaUtils.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/IR/DiagnosticInfo.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
#define DEBUG_TYPE "xtensa-isel"
namespace {
class XtensaDAGToDAGISel : public SelectionDAGISel {
public:
XtensaDAGToDAGISel(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISel(TM, OptLevel) {}
void Select(SDNode *Node) override;
// For load/store instructions generate (base+offset) pair from
// memory address. The offset must be a multiple of scale argument.
bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset,
int Scale) {
EVT ValTy = Addr.getValueType();
// if Address is FI, get the TargetFrameIndex.
if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy);
return true;
}
if (TM.isPositionIndependent()) {
DiagnosticInfoUnsupported Diag(CurDAG->getMachineFunction().getFunction(),
"PIC relocations are not supported ",
Addr.getDebugLoc());
CurDAG->getContext()->diagnose(Diag);
}
if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress))
return false;
// Addresses of the form FI+const
bool Valid = false;
if (CurDAG->isBaseWithConstantOffset(Addr)) {
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
int64_t OffsetVal = CN->getSExtValue();
Valid = isValidAddrOffset(Scale, OffsetVal);
if (Valid) {
// If the first operand is a FI, get the TargetFI Node
if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
else
Base = Addr.getOperand(0);
Offset =
CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy);
return true;
}
}
// Last case
Base = Addr;
Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType());
return true;
}
bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) {
return selectMemRegAddr(Addr, Base, Offset, 1);
}
bool selectMemRegAddrISH2(SDValue Addr, SDValue &Base, SDValue &Offset) {
return selectMemRegAddr(Addr, Base, Offset, 2);
}
bool selectMemRegAddrISH4(SDValue Addr, SDValue &Base, SDValue &Offset) {
return selectMemRegAddr(Addr, Base, Offset, 4);
}
// Include the pieces autogenerated from the target description.
#include "XtensaGenDAGISel.inc"
}; // namespace
class XtensaDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
public:
static char ID;
XtensaDAGToDAGISelLegacy(XtensaTargetMachine &TM, CodeGenOptLevel OptLevel)
: SelectionDAGISelLegacy(
ID, std::make_unique<XtensaDAGToDAGISel>(TM, OptLevel)) {}
StringRef getPassName() const override {
return "Xtensa DAG->DAG Pattern Instruction Selection";
}
};
} // end anonymous namespace
char XtensaDAGToDAGISelLegacy::ID = 0;
FunctionPass *llvm::createXtensaISelDag(XtensaTargetMachine &TM,
CodeGenOptLevel OptLevel) {
return new XtensaDAGToDAGISelLegacy(TM, OptLevel);
}
void XtensaDAGToDAGISel::Select(SDNode *Node) {
SDLoc DL(Node);
// If we have a custom node, we already have selected!
if (Node->isMachineOpcode()) {
Node->setNodeId(-1);
return;
}
SelectCode(Node);
}
|
