1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -run-pass=machine-scheduler %s -o - | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
define i32 @test_add(ptr %0) #0 {
%2 = ptrtoint ptr %0 to i64
%3 = and i64 %2, -64
%4 = inttoptr i64 %3 to ptr
%5 = load i32, ptr %4, align 64
%6 = getelementptr inbounds i32, ptr %4, i64 1
%7 = load i32, ptr %6, align 4
%8 = add nsw i32 %7, %5
ret i32 %8
}
attributes #0 = { "target-cpu"="ampere1" }
...
---
name: test_add
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64, preferred-register: '' }
- { id: 1, class: gpr64sp, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32, preferred-register: '' }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
body: |
bb.0 (%ir-block.1):
liveins: $x0
; CHECK-LABEL: name: test_add
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[ANDXri:%[0-9]+]]:gpr64sp = ANDXri [[COPY]], 7865
; CHECK-NEXT: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ANDXri]], 0 :: (load (s32) from %ir.4, align 64)
; CHECK-NEXT: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ANDXri]], 1 :: (load (s32) from %ir.6)
; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = nsw ADDWrr [[LDRWui1]], [[LDRWui]]
; CHECK-NEXT: $w0 = COPY [[ADDWrr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:gpr64 = COPY $x0
%1:gpr64sp = ANDXri %0, 7865
%2:gpr32 = LDRWui %1, 0 :: (load (s32) from %ir.4, align 64)
%3:gpr32 = LDRWui %1, 1 :: (load (s32) from %ir.6)
%4:gpr32 = nsw ADDWrr %3, %2
$w0 = COPY %4
RET_ReallyLR implicit $w0
...
|
